36.5.8 ASI System Control A
| Name: | ASI_SYS_CTRLA |
| Offset: | 0x0A |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| UROWDONE | CLKREQ | ||||||||
| Access | - | - | - | - | - | - | R/W | R/W | |
| Reset | 0 | 0 |
Bit 1 – UROWDONE User Row Programming Done
Write this bit when the user row data is written to the RAM. Writing a
‘1’ to this bit will start the process of programming the
user row data to the Flash.
If this bit is written before the user row data is written to the RAM by the UPDI, the CPU will proceed without the written data.
This bit is writable only if the USERROW-Write key is successfully decoded.
Bit 0 – CLKREQ Request System Clock
If this bit is written to ‘1’, the ASI is requesting the system
clock, independent of the system’s sleep modes. This makes it possible for the
UPDI to access the ACC layer even if the system is in a sleep mode.
Writing a ‘0’ to this bit will lower the clock
request.
This bit is set by default when the UPDI is enabled in any mode (Fuse, HV).