2.1 Connections Required for ICSP

For ICSP operations, the device must be powered using all power and ground pins available on the package. The device internal circuits are powered from a core voltage regulator (buck converter). The buck converter requires two external components: 10 µH inductor and 4.7 µF ceramic capacitors which should be connected to V_DDCOREand L_X pins as shown in Figure 2-1.

In addition to the power pins, the programming interface includes the MCLR (Reset) and one ICSP programming pin pair (PGEDx/PGECx). All dsPIC33AK256MPS306 devices have three separate pairs of programming pins, labeled as PGEC1/PGED1, PGEC2/PGED2 and PGEC3/PGED3. Table 2-1 explains details about the required connections.

Figure 2-1. Buck Converter Components Connection

Table 2-1. Pins Used for Programming
Pin Name	Pin Type	Description
V_DD/AV_DD	Power	Power supply. Must be in 4.5V-5.5V range, and all power pins must be connected. 0.1 µF bypass capacitors should be connected to these pins.
V_SS/AV_SS	Power	Ground (GND). All ground pins must be connected.
L_X	Buck converter	10 µH inductor must be connected between L_X and V_DDCORE pins.
V_DDCORE	Buck converter	4.7 µF capacitor should be connected between V_DDCORE pin and ground. 10 µH inductor must be connected between L_X and V_DDCORE pins.
SWV_DD	Buck converter	Connect to V_DD/AV_DD.
SWV_SS	Buck converter	Connect to GND, between 4.7 µF capacitor and GND on V_DDCORE pin.
MCLR	Input	Target device Reset/programming enable.
PGECx	Input	ICSP programming clock, where ‘x’ is the programming pair number.
PGEDx	Input/Output	ICSP programming data, where ‘x’ is the programming pair number.

CMOS logic thresholds apply to MCLR and the PGECx/PGEDx signals as specified in Table 2-2.

Table 2-2. Electrical Specification for the Programming Interface Signals
Parameter	Min.	Max.	Description
V_IL	V_SS	0.2 * V_DD	Input low-level voltage
V_IH	0.8 * V_DD	V_DD	Input high-level voltage

For all ICSP operations clocking data into the target device, the PGEDx Output state must be valid and stable before the PGECx clock rising edges. All PGEDx data must be presented with the Least Significant bit (LSb) first.

Figure 2-2, Figure 2-3 and Table 2-3 specify the timing for the ICSP interface signals.

Figure 2-2. ICSP™ Interface Signals Timing Parameters (Programmer Driving PGEDx Pin)

Figure 2-3. ICSP™ Interface Signals Timing Parameters (Target Device Driving PGEDx Pin)

Table 2-3. ICSP™ Interface Signals Timing Parameters
Parameter	Min.	Max.	Description
TD_setup	20 nS	—	Minimum PGEDx data setup time before PGECx rising edge
TD_hold	1 nS	—	Minimum PGEDx data hold time after PGECx rising edge
TC_period	60 nS	—	Minimum PGECx clock period
TC_low or TC_high	20 nS	—	Minimum PGECx clock low or high pulse width
TD_delay	—	20 nS	Maximum data update delay after PGECx falling edge

Figure 2-4 through Figure 2-6 provide the pin diagrams for the different packages of the dsPIC33AK256MPS306 devices. The detailed pin descriptions can be found in the device data sheet.

Figure 2-4. 36-Pin VQFN/TQFP

Figure 2-5. 48-Pin VQFN/TQFP

Figure 2-6. 64-Pin TQFP