1.25.20 SDRAM Controller (SDRAMC)

The SDRAM Controller (SDRAMC) extends the memory capabilities of a chip by providing the interface to the external 16-bit and 32-bit DRAM devices.

The page size supports ranges from 2048 to 8192 and the number of columns from 256 to 2048. It also supports byte (8-bit), half-word (16-bit), and word (32-bit) accesses.

The SDRAMC supports a read or write burst length of one location. It keeps track of the active row in each bank, maximizing SDRAM performance, e.g., the application may be placed in one bank and data in the other banks. For optimized performance, it is advisable to avoid accessing different rows in the same bank.

The SDRAMC supports a CAS latency of 2 or 3 and optimizes the read access depending on the frequency.

The SDRAM controller supports Self-refresh, Power-down and Deep Power-down modes to minimize power consumption on the SDRAM device.

Using The Library

The SDRAMC controller is initialized as configured in the MHC as part of System Initialization.

Library Interface

SDRAM Controller peripheral library provides the following interfaces:

Functions

Name	Description
SDRAMC_Initialize	Initializes and Enables the SDRAM Controller