1.30.5 Direct Memory Access Controller (DMAC)
The DMA Controller (DMAC) can transfer data between memories and peripherals, and thus off-load these tasks from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees up CPU time. With access to all peripherals, the DMAC can handle automatic transfer of data between communication modules. DMAC has several DMA channels and each channel is fully programmable and provides both peripheral or memory-to-memory transfers.
The DMA Controller can also be used to generate CRC on the data been transferred through the channel or an I/O interface.
Using The Library
DMA controller requires source address, destination address and transfer count to initiate transfer. It transfers data on each DMA trigger and decrements the transfer count. The DMA generates completion interrupt to notify CPU at the end of the DMA transfer.
User can use either callback mechanism or polling mechanism to determine DMA completion.
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With polling, the application will need to continuously poll to check if the DMA has completed the transfer.
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With callback, the registered callback function will be called when the transfer is completed. This means the application do not have to poll continuously.
Callback method
This example demonstrates DMA transfer with callback
#define USART1_TRANSMIT_ADDRESS (&SERCOM4_REGS->USART.DATA) uint8_t txBuffer[] = "Hello World!"; void DMAC_Callback(DMAC_TRANSFER_EVENT status, uintptr_t context) { if(status == DMAC_TRANSFER_EVENT_COMPLETE) { // Transfer is completed. } } int main ( void ) { SYS_Initialize ( NULL ); DMAC_ChannelCallbackRegister(DMAC_CHANNEL_0, DMAC_Callback, 0); DMAC_ChannelTransfer(DMAC_CHANNEL_0, txBuffer, (const void *)USART1_TRANSMIT_ADDRESS, sizeof(txBuffer)); }
Polling method
This example demonstrates DMA transfer with polling
#define USART1_TRANSMIT_ADDRESS (&SERCOM4_REGS->USART.DATA) uint8_t txBuffer[] = "Hello World!"; int main ( void ) { SYS_Initialize ( NULL ); DMAC_ChannelTransfer(DMAC_CHANNEL_0, txBuffer, (const void *)USART1_TRANSMIT_ADDRESS, sizeof(txBuffer)); while(DMAC_ChannelIsBusy(DMAC_CHANNEL_0)); }
Library Interface
Direct Memory Access Controller peripheral library provides the following interfaces:
Functions
Name | Description |
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DMAC_Initialize | Initializes the DMAC controller of the device |
DMAC_ChannelCallbackRegister | This function allows a DMAC PLIB client to set an event handler |
DMAC_ChannelTransfer | Schedules a DMA transfer on the specified DMA channel |
DMAC_ChannelIsBusy | The function returns the busy status of the channel |
DMAC_ChannelTransferStatusGet | Returns the DMA channel's transfer status |
DMAC_ChannelDisable | The function disables the specified DMAC channel |
DMAC_ChannelGetTransferredCount | Returns transfer count of the ongoing DMAC transfer |
DMAC_ChannelSuspend | This function Suspends the DMA channel |
DMAC_ChannelResume | This function Resumes the DMA channel |
DMAC_LinkedListDescriptorSetup | Sets up linked list descriptor |
DMAC_ChannelLinkedListTransfer | The function submit a list of DMA transfers |
DMAC_ChannelSettingsGet | Returns the current channel settings for the specified DMAC Channel |
DMAC_ChannelSettingsSet | Changes the current transfer settings of the specified DMAC channel |
DMAC_ChannelCRCSetup | DMA Channel CRC setup and enable function |
DMAC_CRCRead | DMA CRC read function |
DMAC_CRCCalculate | Function to calculate CRC using I/O Interface |
DMAC_CRCDisable | DMA CRC disable function |
Data types and constants
Name | Type | Description |
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DMAC_CHANNEL | Enum | Lists the set of channels available for data transfer using DMAC |
DMAC_TRANSFER_EVENT | Enum | Enumeration of possible DMAC transfer events |
DMAC_CRC_POLYNOMIAL_TYPE | Enum | Enumeration of Supported CRC polynomials |
DMAC_CRC_BEAT_SIZE | Enum | Enumeration of Supported CRC Beat Size |
DMAC_CRC_SETUP | Struct | Fundamental data object that represents DMA CRC setup parameters |
DMAC_CHANNEL_CALLBACK | Typedef | Pointer to a DMAC Transfer Event handler function |
DMAC_CHANNEL_CONFIG | Typedef | DMAC Block Transfer Control configuration value |