3.8.3 Clock Generator (CLOCK)

The Clock Generator is made up of:

  • Oscillators

    • A low-power 32.768 kHz oscillator supporting crystals, MEMs, resonators and Bypass mode

    • An embedded always-on, slow RC oscillator generating a typical 32 kHz clock

    • A 12 to 48 MHz oscillator supporting crystals, MEMs, resonators and Bypass mode

    • A Main RC oscillator generating a typical 12 MHz clock

  • Three fractional-N PLLs

It provides the following clocks:

  • MD SCLK - Monitoring Domain Slow clock, This clock sourced from the always-on Slow RC oscillator only, is the only permanent clock of the system and feeds safety-critical functions of the device.

  • TD SCLK - Timing Domain Slow clock. This clock, sourced from the 32. 768 kHz crystal oscillator or the always-on Slow RC oscillator, is routed to the RTC and RTT peripherals.

  • MAINCK - Output of the Main clock oscillator selection. This clock is either the Main crystal oscillator or Main RC oscillator.

  • PLL Clocks - Outputs of embedded PLLs

  • One SysTick external clock for each processor core

Using The Library

The Clock peripheral library initializes the clock system as configured by the user in the MCC easy view.

Library Interface

Clock Generator peripheral library provides the following interfaces:

Functions

NameDescription
CLK_InitializeInitializes hardware of the System Clock and Peripheral Clock
CLK_TDSCLKSelectXTALSelects 32KHz Crystal Oscillator as Slow Clock (SLCK) source
CLK_EnableMainRCOscillatorEnables main RC oscillator
CLK_DisableMainRCOscillatorDisables main RC oscillator
CLK_EnableMainXTALOscillatorEnables main XTAL oscillator
CLK_DisableMainXTALOscillatorDisables main XTAL oscillator
CLK_MainOscillatorSelectXTALSelects XTAL as main oscillator source
CLK_MainOscillatorSelectRCSelects RC oscillator as main coscillator source
CLK_PLLEnableEnables PLL
CLK_PLLDisableDisbales PLL
CLK_PLLConfigConfigures given PLL parameters
CLK_Core0ClkConfigConfigures core 0 clock parameters
CLK_Core1BusMasterClkEnableEnables core 1 master clock
CLK_Core1BusMasterClkDisableDisables core 1 master clock
CLK_Core1ClkConfigConfigures core 1 clock parameters
CLK_Core1ProcessorClkEnableEnables core 1 processor clock
CLK_Core1ProcessorClkDisableDisables core 1 processor clock
CLK_PCKConfigConfigures programmable clock parameters
CLK_PCKOutputEnableEnables PCK output
CLK_PCKOutputDisableDisables PCK output
CLK_PeripheralClockConfigGetReads peripheral clock parameters
CLK_PeripheralClockConfigSetConfigures peripheral clock parameters