2.1 Multicycle Instructions

As shown in the instruction summary tables, most instructions execute in a single cycle with the following exceptions:

  • ASRM, LSRM, ED, EDAC and a few other instructions require two cycles to execute.
  • Instructions, DIVF, DIVFL, DIVU, DIVUL, DIVS, and DIVSL are single-cycle instructions, which should be executed consecutive times as the target of a REPEAT instruction.
  • Instructions that change the Program Counter require two cycles to execute. Instructions such as CALL also require two cycles to execute.
  • RETFIE , RETLW and RETURN are a special case of an instruction that changes the Program Counter. These execute in three to four cycles, unless an exception is pending, and then they execute in two cycles.

The cycle count of program flow change instructions also depend on the status of PBU cache. The table below shows the cycle counts of these instructions under different scenarios.

Table 2-2. Program Flow Control and Instruction Execution Times
InstructionCycle Counts
Cache/ISB HitCache/ISB MissExecution from RAM
Conditional Branch11 (3) 1 (6 to 9)1 (3)
BRA14–71
BRA W5–85-82
CALL14–71
CALL W5–85–82
GOTO 14–71
GOTO W5–85–82
RCALL14–71
RCALL W5–85–82
RETFIE7–107–104
RETLW6–96–93
RETURN6–96–93
Note:
  1. Branch taken execution times in ( ) brackets.