27.3.2.3.1.1 Case S1: Address
Packet Accepted - Direction Bit Set to ‘0’
If an ACK is sent by the slave after the
address packet is received and the Read/Write Direction (DIR) bit in the Slave Status
(TWIn.SSTATUS) register is set to ‘0’, the master indicates a write
operation.
The clock hold is active at this point, forcing the SCL low. This will stretch the low period of the clock to slow down the overall clock frequency, forcing delays required to process the data and preventing further activity on the bus.
The software can prepare to:
- Read the received data packet from the master