34.3.2.1.3 UPDI Enable with High-Voltage Override of RESET Pin
- Recommended: Reset the device before starting the HV enable sequence.
- Apply the HV signal, as described in the figure below.
- Send the NVMPROG key using the
key
instruction after the first SYNC character. - After the programming is
finished, reset the UPDI by writing the UPDI Disable (UPDIDIS) bit in the
Control B (UPDI.CTRLB) register to ‘
1
’ using theSTCS
instruction.
During power-up, the Power-on Reset (POR) must be released before the HV pulse can be applied. The duration of the pulse is recommended in the range from 100 μs to 1 ms before tri-stating.
When applying the rising edge of the HV pulse, the UPDI will be reset. After tri-stating the UPDI will remain in Reset until the RESET pin is driven low by the debugger. This will release the UPDI Reset, and initiate the same enable sequence as explained in 34.3.2.1.2 UPDI Enable with Fuse Override of RESET Pin.
When enabled by an HV pulse, only a POR will disable the UPDI configuration on the RESET pin and restore the default setting. If issuing a UPDI Disable command through the UPDIDIS bit in UPDI.CTRLB, the UPDI will be reset, and the clock request will be canceled, but the RESET pin will remain in UPDI configuration.