34.3.2.1.2 UPDI Enable with Fuse Override of RESET Pin

When the RESET Pin Configuration (RSTPINCFG) bit in FUSE.SYSCFG0 is 0x1, the RESET pin will be overridden, and the UPDI will take control of the pin and configure it as an input with pull-up. When the pull-up is detected by a connected debugger, the UPDI enable sequence, as depicted below, is started.

When the pull-up is detected, the debugger initiates the enable sequence by driving the line low for a duration of T_Deb0.

The negative edge is detected by the UPDI, which starts the UPDI clock. The UPDI will continue to drive the line low until the clock is stable and ready for the UPDI to use. The duration of T_UPDI will vary, depending on the status of the oscillator when the UPDI is enabled. After this duration, the data line will be released by the UPDI and pulled high.

When the debugger detects that the line is high, the initial SYNCH character (0x55) must be transmitted to synchronize the UPDI communication data rate. If the Start bit of the SYNCH character is not sent within maximum T_DebZ, the UPDI will disable itself, and the UPDI enabling sequence must be reinitiated. The UPDI is disabled if the timing is violated to avoid the UPDI being enabled unintentionally.

After successful SYNCH character transmission, the first instruction frame can be transmitted.