22 Errata

DSU

Reference:16144

When the device is waking from standby retention mode, selected alternate function on PA30 (SERCOM for example) will be lost, and it functions as SWCLK pin and can switch the device to debug mode.

Workaround

Disable the debugger Hot-Plugging detection by setting the security bit. Security is set by issuing the NVMCTRL SSB command.

Affected Silicon Revisions


C
X

DFLL48M

Reference:9905

The DFLL clock must be requested before being configured, otherwise, a write access to a DFLL register can freeze the device.

Workaround

Write a ‘0’ to the DFLL ONDEMAND bit in the DFLLCTRL register before configuring the DFLL module.

Affected Silicon Revisions


C
X

Reference:16192

If the DFLL48M reaches the maximum or minimum COARSE or FINE calibration values during the locking sequence, an out-of-bounds interrupt will be generated. These interrupts will be generated even if the final calibration values at DFLL48M lock are not at maximum or minimum, and might, therefore, be false out of bounds interrupts.

Workaround

Check that the lockbits: DFLLLCKC and DFLLLCKF in the OSCCTRL Interrupt Flag Status and Clear register (INTFLAG) are both set before enabling the DFLLOOB interrupt.

Affected Silicon Revisions


C
X

Reference:16193

The DFLL status bits in the STATUS register during the USB clock recovery mode can be wrong after a USB suspend state.

Workaround

Do not monitor the DFLL status bits in the STATUS register during the USB clock recovery mode.

Affected Silicon Revisions


C
X

DMAC

Reference:15670

When using more than one DMA channel, and if one of these DMA channels has a linked descriptor, a fetch error can appear on this channel.

Workaround

Do not use linked descriptors, make a software link instead:

Replace the channel that used the linked descriptor with two-channel DMA (with the linked descriptor disabled) handled by the two channels event system:

DMA channel 0 transfer completion is able to send a conditional event for DMA channel 1 (via event system with configuration of BTCTRL.EVOSEL = BLOCK for channel 0 and configuration CHCTRLB.EVACT = CBLOCK for channel 1).
On the transfer complete reception of DMA channel 0, immediately re-enable channel 0.
Then, DMA channel 1 transfer completion is able to send a conditional event for DMA channel 0 (via event system with configuration of BTCTRL.EVOSEL = BLOCK for channel 1 and configuration CHCTRLB.EVACT = CBLOCK for channel 0).
On the transfer complete reception of DMA channel 1, immediately re-enable the channel 1.
The mechanism can be launched by sending a software event on DMA channel 0.

Affected Silicon Revisions


C
X

Reference:15683

When at least one channel using linked descriptors is already active, enabling another DMA channel (with or without linked descriptors) can result in a channel Fetch Error (FERR) or an incorrect descriptor fetch.

Workaround

This happens if the channel number of the channel being enabled is lower than the channel already active.

When enabling a DMA channel while other channels using linked descriptors are already active, the channel number of the new channel enabled must be greater than the other channel numbers.

Affected Silicon Revisions


C
X

FDPLL

Reference:15753

When the FDPLL ratio value in the DPLLRATIO register is changed on the fly, STATUS.DPLLLDRTO will not be set even though the ratio is updated.

Workaround

Monitor the INTFLAG.DPLLLDRTO instead of STATUS.DPLLLDRTO to get the status for the DPLLRATIO update.

Affected Silicon Revisions


C
X

PORT

Reference:15611

PORT read/write attempts on non-implemented registers, including addresses beyond the last implemented register group (PA, PB,...) do not generate a PAC protection error.

Workaround

None

Affected Silicon Revisions


C
X

EIC

Reference:14417

Access to EIC_ASYNCH register in 8/16-bit mode is not functional.

Workaround

Writing in 8-bit mode will also write this byte in all bytes of the 32-bit word.
Writing the higher 16 bits will also write the lower 16 bits.
Writing the lower 16 bits will also write the higher 16 bits.

Two workarounds are available:

Use 32-bit write mode.
Write only the lower 16 bits. (This will write the upper 16 bits also, but does not impact the application.)

Affected Silicon Revisions


C
X

Reference:15278

When the EIC is configured to generate an interrupt on a low level or rising edge or both edges (CONFIGn.SENSEx) with the filter enabled (CONFIGn.FILTENx), a spurious flag might appear for the dedicated pin on the INTFLAG.EXTINT[x] register as soon as the EIC is enabled using CTRLA ENABLE bit.

Workaround

Clear the INTFLAG bit once the EIC enabled and before enabling the interrupts.

Affected Silicon Revisions


C
X

Reference:15279

Changing the NMI configuration (CONFIGn.SENSEx) on the fly may lead to a false NMI interrupt.

Workaround

Clear the NMIFLAG bit once the NMI is modified.

Affected Silicon Revisions


C
X

Reference:16103

When the asynchronous edge detection is enabled and the system is in standby mode, only the first edge will generate an event. The following edges will not generate events until the system wakes up.

Workaround

Asynchronous edge detection does not work, instead, use the synchronous edge detection (ASYNCH.ASYNCH[x] = 0). In order to reduce power consumption when using synchronous edge detection, either set the GCLK_EIC frequency as low as possible or select the ULP32K clock (EIC CTRLA.CKSEL = 1).

Affected Silicon Revisions


C
X

Device

Reference:15581

On pin PA24 and PA25, the pull-up and pull-down configuration is not disabled automatically when alternative pin function is enabled.

Workaround

For pin PA24 and PA25, the GPIO pull-up and pull-down must be disabled before enabling alternative functions on them.

Affected Silicon Revisions


C
X

Reference:16225

When configured in HS or FastMode+, SDA and SCL fall times are shorter than the I²C specification requirement and can lead to reflection.

Workaround

When reflection is observed, a 100 ohms serial resistor can be added on the impacted line.

Affected Silicon Revisions


C
X

ADC

Reference:14431

The LSB of ADC result is stuck at zero, in unipolar mode for 8-bit and 10-bit resolution.

Workaround

Use the 12-bit resolution and take only at least 8 bits or 10 bits, if necessary.

Affected Silicon Revisions


C
X

Reference:15463

In standby sleep mode, when the ADC is in free-running mode (CTRLC.FREERUN = 1) and the RUNSTDBY bit is set to 0 (CTRLA.RUNSTDBY = 0), the ADC keeps requesting its generic clock.

Workaround

Stop the free-running mode (CTRLC.FREERUN = 0) before entering standby sleep mode

Affected Silicon Revisions


C
X

Reference:16027

ADC SYNCBUSY.SWTRIG gets stuck to ‘1’ after wake-up from standby sleep mode.

Workaround

Ignore ADC SYNCBUSY.SWTRIG status when waking up from standby sleep mode. The ADC result can be read after INTFLAG.RESRDY is set. To start the next conversion, write ‘1’ to SWTRIG.START.

Affected Silicon Revisions


C
X

TC

Reference:15056

When clearing the STATUS.PERBUFV/STATUS.CCBUFx flag, SYNCBUSY flag is released before the PERBUF/CCBUFx register is restored to its appropriate value.

Workaround

Clear successively twice the STATUS.PERBUFV/STATUS.CCBUFx flag to ensure that the PERBUF/CCBUFx register value is properly restored before updating it.

Affected Silicon Revisions


C
X

TCC

Reference:14817

Advance capture mode (CAPTMIN CAPTMAX LOCMIN LOCMAX DERIV0) does not work if an upper channel is not in one of these modes. Example: when CC[0] = CAPTMIN, CC[1] = CAPTMAX, CC[2] = CAPTEN and CC[3] = CAPTEN, CAPTMIN and CAPTMAX will not work.

Workaround

Basic capture mode must be set in a lower channel and advance capture mode in an upper channel.

Example: CC[0] = CAPTEN , CC[1] = CAPTEN , CC[2] = CAPTMIN, CC[3] = CAPTMAX

All capture will be done as expected.

Affected Silicon Revisions


C
X

Reference:15057

When clearing STATUS.xxBUFV flag, SYNCBUSY is released before the register is restored to its appropriate value.

Workaround

To ensure that the register value is properly restored before updating this same register through xx or xxBUF with a new value, the STATUS.xxBUFV flag must be cleared successively two times.

Affected Silicon Revisions


C
X

Reference:15625

Using TCC in dithering mode with external retrigger events can lead to an unexpected stretch of right-aligned pulses or shrink of left-aligned pulses.

Workaround

Do not use retrigger events/actions when TCC is configured in dithering mode.

Affected Silicon Revisions


C
X

EVSYS

Reference:14532

Using synchronous, spurious overrun can appear with a generic clock for the channel always on.

Workaround

Request the generic clock on demand by setting the CHANNEL.ONDEMAND bit to ‘1’.
No penalty is introduced.

Affected Silicon Revisions


C
X

Reference:14835

The acknowledge between an event user and the EVSYS clears the CHSTATUS.CHBUSYn bit before this information is fully propagated in the EVSYS one GCLK_EVSYS_CHANNEL_n clock cycle later. As a consequence, any generator event occurring on that channel before that extra GCLK_EVSYS_CHANNEL_n clock cycle will trigger the overrun flag.

Workaround

For applications using event generators other than the software event, monitor the OVR flag.

For applications using the software event generator, wait one GCLK_EVSYS_CHANNEL_n clock cycle after the CHSTATUS.CHBUSYn bit is cleared before issuing a software event.

Affected Silicon Revisions


C
X

SERCOM

Reference:13852

In USART autobaud mode, missing stop bits are not recognized as inconsistent sync (ISF) or framing (FERR) errors.

Workaround

None

Affected Silicon Revisions


C
X