Features
- Processor
- ARM Cortex-M0+ CPU running at
up to 48 MHz
- Single-cycle hardware multiplier
- Micro Trace Buffer (MTB)
- ARM Cortex-M0+ CPU running at
up to 48 MHz
- Memories
- 256 KB in-system self-programmable Flash
- 32 KB SRAM main memory
- 8 KB SRAM low power memory
- System
- Power-on reset (POR) and brown-out detection (BOD)
- Internal and external clock options with 48 MHz Digital Frequency Locked Loop (DFLL48M) and 48 MHz to 96 MHz Fractional Digital Phase Locked Loop (FDPLL96M)
- External Interrupt Controller (EIC)
- Up to 16 external interrupts
- One non-maskable interrupt
- Two-pin Serial Wire Debug (SWD) programming, test and debugging interface
- Low Power
- Idle and standby sleep modes
- SleepWalking peripherals
- Integrated Ultra Low Power
Transceiver for 700/800/900 MHz ISM Band:
- Chinese WPAN band from 779 to 787 MHz
- European SRD band from 863 to 870 MHz
- North American ISM band from 902 to 928 MHz
- Japanese band from 915 to 930 MHz
- Direct Sequence Spread Spectrum with
different modulation and data rates:
- BPSK with 20 and 40 kb/s, compliant to IEEE® 802.15.4-2003/2006/2011
- O-QPSK with 100 and 250 kb/s, compliant to IEEE 802.15.4-2006/2011
- O-QPSK with 250 kb/s, compliant to IEEE 802.15.4-2011
- O-QPSK with 200, 400, 500 and 1000 kb/s PSDU data rate
- Industry leading link budget:
- RX Sensitivity up to -110 dBm
- TX Output Power up to +11 dBm
- Hardware Assisted MAC
- Auto-Acknowledge
- Auto-Retry
- CSMA-CA and Listen Before Talk (LBT)
- Automatic address filtering and automated FCS check
- Special IEEE
802.15.4™-2011 hardware support:
- FCS computation and Clear Channel Assessment
- RSSI measurement, Energy Detection and Link Quality Indication
- Antenna Diversity and PA/LNA Control
- 128-Byte TX/RX Frame Buffer
- Integrated 16 MHz Crystal Oscillator (external crystal needed)
- Fully integrated, fast settling Transceiver PLL to support Frequency Hopping
- Hardware Security (AES, True Random Generator)
- Peripherals
- 16-channel Direct Memory Access Controller (DMAC)
- 12-channel Event System
- Up to three 16-bit
Timer/Counters (TC), configurable as either:
- 16-bit TC with compare/capture channels
- 8-bit TC with compare/capture channels
- One 32-bit TC with compare/capture channels, by using two TCs
- Two 24-bit and one 16-bit
Timer/Counters for Control (TCC), with extended functions:
- Up to four compare channels with optional complementary output
- Generation of synchronized pulse width modulation (PWM) pattern across port pins
- Deterministic fault protection, fast decay and configurable dead-time between complementary output
- Dithering that increase resolution with up to 5-bit and reduce quantization error
- 32-bit Real Time Counter (RTC) with clock/calendar function
- Watchdog Timer (WDT)
- CRC-32 generator
- One full-speed (12 Mbps)
Universal Serial Bus (USB) 2.0 interface
- Embedded host and device function
- Eight endpoints
- Up to five Serial Communication Interfaces (SERCOM), each configurable to
operate as either:
- USART with full-duplex and single-wire half-duplex configuration
- I2C up to 3.4 MHz
- SPI
- LIN slave
- One 12-bit, 1 MSPS
Analog-to-Digital Converter (ADC) with up to eight external channels
- Differential and single-ended input
- Automatic offset and gain error compensation
- Oversampling and decimation in hardware to support 13-, 14-, 15- or 16-bit resolution
- Two Analog Comparators (AC) with window compare function
- Peripheral Touch Controller (PTC)
- 18-channel capacitive touch and proximity sensing
- Wake-up on touch in standby mode
- I/O and Package
- 16/28 programmable I/O pins
- 32-pin and 48-pin QFN
- Operating Voltage
- 1.8V – 3.6V
- Temperature Range
- -40°C to 85°C Industrial
- Power Consumption
- Transceiver with
microcontroller in idle mode (TX output power +5 dBm):
- RX_ON = 9.4 mA
- BUSY_TX = 18.2 mA
- Active mode for the microcontroller down to 60 μA/MHz
- Standby mode for the microcontroller down to 1.4 μA/MHz
- Transceiver with
microcontroller in idle mode (TX output power +5 dBm):