3 Signal Description
The following table gives details on signal names classified by peripheral.
| Signal Name | Function | Type | Comments | Active Level |
|---|---|---|---|---|
| Clocks, Oscillators and PLLs | ||||
| XIN | Main Crystal Oscillator Input | Input | – | – |
| XOUT | Main Crystal Oscillator Output | Output | – | – |
| XIN32 | 32.768 kHz Crystal Oscillator Input | Input | – | – |
| XOUT32 | 32.768 kHz Crystal Oscillator Output | Output | – | – |
| RTUNE | USB External Resistor | Analog | – | – |
| PCK[1:0] | Programmable Clock Output | Output | – | – |
| Shutdown, Wakeup Logic | ||||
| SHDN | Shutdown Control | Output | – | – |
| WKUP[13:0] | Wake-Up Inputs | Input | – | – |
| ICE and JTAG | ||||
| TCK | Test Clock | Input | – | – |
| TDI | Test Data In | Input | – | – |
| TDO | Test Data Out | Output | – | – |
| TMS | Test Mode Select | Input | – | – |
| JTAGSEL | JTAG Selection | Input | – | – |
| RTCK | Return Test Clock | Output | – | |
| Reset/Test | ||||
| NRST | External nReset Input | Input | – | Low |
| NRST_OUT | Reset Controller Output | Output | – | Low |
| NTRST | Test Reset Signal | Input | – | |
| Debug Unit - DBGU | ||||
| DRXD | Debug Receive Data | Input | – | – |
| DTXD | Debug Transmit Data | Output | – | – |
| Advanced Interrupt Controller - AIC | ||||
| EXT_IRQ | External Interrupt Input | Input | – | – |
| EXT_FIQ | Fast Interrupt Input | Input | – | – |
| PIO Controller - PIOA - PIOB - PIOC - PIOD | ||||
| PA[31:0] | Parallel IO Controller A | I/O | – | – |
| PB[25:0] | Parallel IO Controller B | I/O | – | – |
| PC[31:0] | Parallel IO Controller C | I/O | – | – |
| PD[21:0] | Parallel IO Controller D | I/O | – | – |
| External Bus Interface - EBI | ||||
| D[15:0] | Data Bus | I/O | – | – |
| D[31:16] | Data Bus | I/O | – | – |
| A[25:0] | Address Bus | Output | – | – |
| NWAIT | External Wait Signal | Input | – | Low |
| Static Memory Controller - SMC | ||||
| NCS[5:0] | Chip Select Lines | Output | – | Low |
| NWR[3:0] | Write Signal | Output | – | Low |
| NRD | Read Signal | Output | – | Low |
| NWE | Write Enable | Output | – | Low |
| NBS[3:0] | Byte Mask Signal | Output | – | Low |
| NAND Flash Controller | ||||
| NANDCS | NAND Flash Chip Select | Output | – | Low |
| NANDOE | NAND Flash Output Enable | Output | – | Low |
| NANDWE | NAND Flash Write Enable | Output | – | Low |
| NANDALE | NAND Flash Address Latch Enable | Output | – | – |
| NANDCLE | NAND Flash Command Latch Enable | Output | – | – |
| DDR2 / SDRAM / LPDDR / LPSDR Controller | ||||
| SDCK | DRAM Clock | Output | – | – |
| SDCKN | DRAM Clock bar (DDR2 / LPDDR only) | – | ||
| SDCKE | DRAM Clock Enable | Output | – | High |
| SDCS | DRAM Chip Select | Output | – | Low |
| BA[2:0] | Bank Select | Output | – | Low |
| SDWE | DRAM Write Enable | Output | – | Low |
| DDR_VREF | DDR2 I/O Reference Voltage | Input | – | – |
| DDR_CAL | LPDDR / DDR2 Calibration Input | Input | – | – |
| RAS - CAS | Row and Column Signal | Output | – | Low |
| SDA10 | SDRAM Address 10 Line | Output | – | – |
| DQS[1:0] | Positive Data Strobe | I/O | – | – |
| NDSQ[1:0] | Negative Data Strobe | I/O | – | – |
| DQM[3:0] | Write Data Mask | Output | – | – |
| Secure Data Memory Card - SDMMCx [1:0] | ||||
| SDMMCx_CMD | SD Card / e.MMC Command line | I/O | – | – |
| SDMMCx_CK | SD Card / e.MMC Clock Signal | Output | – | – |
| SDMMCx_DAT[3:0] | SD Card / e.MMC Data Lines | I/O | – | – |
| Flexible Serial Communication Controller - FLEXCOMx [12:0] | ||||
| FLEXCOMx_IO0 | TXD / MOSI / TWD | I/O | – | – |
| FLEXCOMx_IO1 | RXD / MISO / TWCK | I/O | – | – |
| FLEXCOMx_IO2 | SCK / SPCK / – | I/O | – | – |
| FLEXCOMx_IO3 | CTS / NPCS0 or NSS / – | I/O | – | – |
| FLEXCOMx_IO4 | RTS / NPCS1 / – | Output | – | – |
| FLEXCOMx_IO5 | – / NPCS2 / – | Output | – | – |
| FLEXCOMx_IO6 | – / NPCS3 / – | Output | – | – |
| FLEXCOMx_IO7 | LONCOL / – / – | Input | – | – |
| Synchronous Serial Controller - SSC | ||||
| TD | SSC Transmit Data | Output | – | – |
| RD | SSC Receive Data | Input | – | – |
| TK | SSC Transmit Clock | I/O | – | – |
| RK | SSC Receive Clock | I/O | – | – |
| TF | SSC Transmit Frame Sync | I/O | – | – |
| RF | SSC Receive Frame Sync | I/O | – | – |
| Image Sensor Interface - ISI | ||||
| ISI_D[11:0] | Image Sensor Data | Input | – | – |
| ISI_MCK | Image sensor Reference Clock | Output | – | – |
| ISI_HSYNC | Image Sensor Horizontal Synchro | Input | – | – |
| ISI_VSYNC | Image Sensor Vertical Synchro | Input | – | – |
| ISI_PCK | Image Sensor Data Clock | Input | – | – |
| Timer / Counter - TCx [5:0] | ||||
| TCLKx | TC Channel x External Clock Input | Input | – | – |
| TIOAx | TC Channel x I/O Line A | I/O | – | – |
| TIOBx | TC Channel x I/O Line B | I/O | – | – |
| Pulse Width Modulation Controller- PWMC | ||||
| PWM[3:0] | Pulse Width Modulation Output | Output | – | – |
| USB Host High Speed Port - UHPHS | ||||
| HHSDMA | USB Host Port A High Speed Data - | Analog | – | – |
| HHSDPA | USB Host Port A High Speed Data + | Analog | – | – |
| HHSDMB | USB Host Port B High Speed Data - | Analog | – | – |
| HHSDPB | USB Host Port B High Speed Data + | Analog | – | – |
| HHSDMC | USB Host Port C High Speed Data - | Analog | – | – |
| HHSDPC | USB Host Port C High Speed Data + | Analog | – | – |
| USB Device High Speed Port - UDPHS | ||||
| DHSDM | USB Device High Speed Data - | Analog | – | – |
| DHSDP | USB Device High Speed Data + | Analog | – | – |
| Ethernet 10/100 - EMAC0 | ||||
| E0_TXCK | Transmit Clock or Reference Clock | Input | – | – |
| E0_RXCK | Receive Clock | Input | – | – |
| E0_TXEN | Transmit Enable | Output | – | – |
| E0_TX[3:0] | Transmit Data | Output | – | – |
| E0_TXER | Transmit Coding Error | Output | – | – |
| E0_RXDV | Receive Data Valid | Input | – | – |
| E0_RX[3:0] | Receive Data | Input | – | – |
| E0_RXER | Receive Error | Input | – | – |
| E0_CRS | Carrier Sense and Data Valid | Input | – | – |
| E0_COL | Collision Detect | Input | – | – |
| E0_MDC | Management Data Clock | Output | – | – |
| E0_MDIO | Management Data Input/Output | I/O | – | – |
| RMII Ethernet 10/100 - EMAC1 | ||||
| E1_REFCK | Transmit Clock or Reference Clock | Input | – | – |
| E1_TXEN | Transmit Enable | Output | – | – |
| E1_TX[1:0] | Transmit Data | Output | – | – |
| E1_CRSDV | Receive Data Valid | Input | – | – |
| E1_RX[1:0] | Receive Data | Input | – | – |
| E1_RXER | Receive Error | Input | – | – |
| E1_MDC | Management Data Clock | Output | – | – |
| E1_MDIO | Management Data Input/Output | I/O | – | – |
| LCD Controller - LCDC | ||||
| LCDDAT[23:0] | LCD Data Bus | Output | – | – |
| LCDVSYNC | LCD Vertical Synchronization | Output | – | – |
| LCDHSYNC | LCD Horizontal Synchronization | Output | – | – |
| LCDPCLK | LCD Pixel Clock | Output | – | – |
| LCDDEN | LCD Data Enable | Output | – | – |
| LCDPWM | LCD Contrast Control | Output | – | – |
| LCDDISP | LCD Display Enable | Output | – | – |
| 12-bit Analog-to-Digital Converter with Resistive Touch - ADC | ||||
| AD0XP_UL | Top/Upper Left Channel | Analog | – | – |
| AD1XM_UR | Bottom/Upper Right Channel | Analog | – | – |
| AD2YP_LL | Right/Lower Left Channel | Analog | – | – |
| AD3YM_SENSE | Left/Sense Channel | Analog | – | – |
| AD4LR | Lower Right Channel | Analog | – | – |
| AD[11:5] | 7 Analog Inputs | Analog | – | – |
| ADTRG | ADC Trigger | Input | – | – |
| ADVREFN | ADC Negative Input Reference Voltage | Analog | – | – |
| ADVREFP | ADC Positive Input Reference Voltage | Analog | – | – |
| CAN Controller - CANx [1:0] | ||||
| CANRXx | CAN Receive | Input | – | – |
| CANTXx | CAN Transmit | Output | – | – |
| Class D Controller - CLASSD | ||||
| CLASSD_L0 | Class D Controller Left Output 0 | Output | – | – |
| CLASSD_L1 | Class D Controller Left Output 1 | Output | – | – |
| CLASSD_L2 | Class D Controller Left Output 2 | Output | – | – |
| CLASSD_L3 | Class D Controller Left Output 3 | Output | – | – |
| Quad I/O SPI - QSPI | ||||
| QSCK | Quad IO SPI Serial Clock | Output | – | – |
| QCS | Quad IO SPI Chip Select | Output | – | – |
| QIO[3:0] | Quad IO SPI I/O 0 to 3 | I/O | – | – |
| Inter IC Sound Multi Channel Controller - I2SMCC | ||||
| I2SMCC_MCK | Main System Bus Clock | Output | – | – |
| I2SMCC_CK | Serial Clock | I/O | – | – |
| I2SMCC_WS | I2S Word Select | I/O | – | – |
| I2SMCC_DIN | Serial Data Input | Input | – | – |
| I2SMCC_DOUT | Serial Data Output | Output | – | – |