Features

CPU running up to 600 MHz

Memories

One 160-Kbyte internal ROM
- 64-Kbyte internal ROM embedding a secure bootloader program supporting boot on NAND Flash, SD Card, SPI or QSPI Flash. Bootloader features selectable by OTP bits
- 96-Kbyte ROM for NAND Flash BCH ECC table
One 64-Kbyte internal SRAM (SRAM0), single-cycle access at system speed
High-bandwidth Multi-port DDR2/LPDDR Controller
32/16-bit External Bus Interface (EBI) supporting 8/4-bank DDR2/LPDDR, 4/2-bank SDR/LPSDR, static memories, with scrambling
NAND Flash Controller, with up to 24-bit Programmable Multi-bit Error Correcting Code
One 11-Kbyte OTP memory for secure key storage with emulation mode (OTP bits are emulated by a 4-Kbyte SRAM (SRAM1))

System Running up to 200 MHz

Power-on reset cells, Reset Controller, Shutdown Controller, Periodic Interval Timer, Watchdog Timer running on internal slow RC oscillator (32 kHz typical) and Real Time Clock running on slow crystal oscillator (32.768 kHz)
Two internal trimmed RC oscillators with typical values: 32 kHz (slow) and 12 MHz (fast)
Two crystal oscillators: 32.768 kHz (slow) and 12 to 48 MHz (fast)
One PLL for the system and one PLL optimized for USB high-speed operation (480 MHz)
One dual-port 16-channel DMA Controller
Advanced Interrupt Controller and Debug Unit
JTAG port with disable bit in OTP memory
Two programmable clock output signals

Low-Power Modes

Backup mode with RTC, eight 32-bit general purpose backup registers, and Shutdown Controller to control the external power supply
Clock Generator and Power Management Controller
Software-programmable ultra-low power modes: Very Slow Clock operating mode (ULP0), and No-Clock operating Mode (ULP1) with fast wake-up capabilities
Software programmable power optimization capabilities

Peripherals

LCD Controller with overlay, alpha-blending, rotation, scaling and color conversion. Up to 1024 x 768 resolution
2D Graphics Controller supporting fill BLT, copy BLT, transparent BLT, blend/alpha BLT, ROP4 BLT (Raster Operations) and command ring buffer
ITU-R BT. 601/656, up to 12-bit Image Sensor Interface
One USB Device High Speed, three USB Host High Speed with dedicated On-Chip Transceivers
Two 10/100 Mbps Ethernet Mac Controller
Two 4-bit Secure Digital MultiMedia Card Controller
Two CAN Controllers
One Quad I/O SPI Controller
Two three-channel 32-bit Timers/Counters
One high resolution (64-bit) Periodic Interval Timer
One Synchronous Serial Controller
One Inter-IC Sound Multi-Channel Controller with TDM support
One Audio Class D Controller with single-ended or bridge-tied load connection to power stage
One four-channel 16-bit PWM Controller
Thirteen FLEXCOMs (USART, SPI and TWI)
One 12-channel 12-bit Analog-to-Digital Converter with 4/5 wires resistive touchscreen support

Hardware Cryptography

SHA (SHA1, SHA224, SHA256, SHA384, SHA512) and HMAC: compliant with FIPS PUB 180-2
AES: 256-, 192-, 128-bit key algorithms, compliant with FIPS PUB 197
TDES: two-key or three-key algorithms, compliant with FIPS PUB 46-3
True Random Number Generator, compliant with NIST Special Publication 800-22 Test Suite and FIPS PUBs 140-2 and 140-3

I/O Ports

Four 32-bit Parallel Input/Output Controllers
Up to 112 programmable I/O lines multiplexed with up to three peripheral I/Os
Input change interrupt capability on each I/O line, optional Schmitt trigger input
Individually programmable open-drain, pull-up and pull-down resistor, synchronous output
General-purpose analog and digital inputs tolerant to positive and negative current injection

Automotive

Package

228-ball TFBGA 11x11 mm², 0.65 mm pitch, optimized for standard class PCB layout (down to four layers)

Design for low ElectroMagnetic Interference (EMI)

Slewrate-controlled I/Os
DDR/SDR Phy with impedance-calibrated drivers
Spread spectrum PLLs
Careful BGA power/ground ball assignment to provide optimum decoupling capacitors placement

Operating Conditions