35.5.2 Control Gear

The Control Gear mode is configured with the following settings:

  • MODE = ‘b1001
  • TXEN = 1
  • RXEN = 1
  • UxP1 = back frames are held for transmission with this number of half-bit periods after the completion of a forward frame
  • UxP2 = forward/back frame threshold delimiter. Idle periods longer than this number of half-bit periods are detected as forward frames.
  • UxBRG = value to achieve 1200 baud rate
  • TXPOL = appropriate polarity for interface circuit
  • RXPOL = same as TXPOL
  • STP = ‘b10 for two Stop bits
  • RxyPPS = TX pin output code
  • TX pin TRIS control = 0
  • RXPPS = RX pin selection code
  • RX pin TRIS control = 1
  • Input pin ANSEL bit = 0
  • ON = 1

The UART starts listening for a forward frame when the Control Gear mode is entered. Only the frames that follow an Idle period longer than UxP2 half-bit periods are detected as forward frames. Backward frames from other Control Gear are ignored. Only forward frames will be stored in UxRXB. This is necessary because a backward frame can be sent only as a response to a forward frame.

The forward frame is received one byte at a time in the receive FIFO and retrieved by reading the UxRXB register. The end of the forward frame starts a timer to delay the backward frame response by a wait time equal to the number of half-bit periods stored in UxP1.

The data received in the forward frame is processed by the application software. If the application decides to send a backward frame in response to the forward frame, the value of the backward frame is written to UxTXB. This value is held for transmission in the transmit shift register until the wait time expires, being transmitted afterwards.

If the backward frame data is written to UxTXB after the wait time has expired, it is held in the UxTXB register until the end of the wait time following the next forward frame. The TXMTIF bit is false when the backward frame data is held in the transmit shift register. Receiving a UxRXIF interrupt before the TXMTIF goes true indicates that the backward frame write was too late and another forward frame was received before sending the backward frame. The pending backward frame is flushed by setting the TXBE bit to prevent it from being sent after the next forward frame.