12.5.4 OSCCON3
Note:
- If CSWHOLD =
0
, the user may not see this bit set (NOSCR =1
). When the oscillator becomes ready, there may be a delay of one instruction cycle before NOSCR is set. The clock switch occurs in the next instruction cycle and NOSCR is cleared.
Name: | OSCCON3 |
Address: | 0x0AF |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
CSWHOLD | SOSCPWR | ORDY | NOSCR | ||||||
Access | R/W/HC | R/W | R | R | |||||
Reset | 0 | 1 | 0 | 0 |
Bit 7 – CSWHOLD Clock Switch Hold Control
Bit 6 – SOSCPWR Secondary Oscillator Power Mode Select
Value | Description |
---|---|
1 | Secondary Oscillator operates in High Power mode |
0 | Secondary Oscillator operates in Low Power mode |