36.6.3.4 Receiver Overflow and Transmitter Underflow Interrupts
The receiver overflow interrupt triggers if data is received when the
receive FIFO is already full and RXR = 1
. In this case, the data will
be discarded and the RXOIF bit will be set. The Receiver Overflow Interrupt Enable bit is RXOIE.
The Transmitter Underflow Interrupt flag triggers if a data transfer begins
when the transmit FIFO is empty and TXR = 1
. In this case, the most
recently received data will be transmitted and the TXUIF bit will be set. The Transmitter Underflow Interrupt Enable bit is
TXUIE.
Both these interrupts will only occur in Client mode, as Host mode will not allow the receive FIFO to overflow or the transmit FIFO to underflow.