36.7.1 SPIxCON0
Note:
SPI Control Register 0- Do not change this bit when
EN =
1
.
Name: | SPIxCON0 |
Address: | 0x084, 0x91 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
EN | LSBF | MST | BMODE | ||||||
Access | R/W | R/W | R/W | R/W | |||||
Reset | 0 | 0 | 0 | 0 |
Bit 7 – EN SPI Enable
Value | Description |
---|---|
1 | SPI is enabled |
0 | SPI is disabled |
Bit 2 – LSBF LSb-First Data Exchange Select(1)
Value | Description |
---|---|
1 | Data is exchanged LSb first |
0 | Data is exchanged MSb first (traditional SPI operation) |
Bit 1 – MST SPI Host Operating Mode Select(1)
Value | Description |
---|---|
1 | SPI module operates as the bus host |
0 | SPI module operates as a bus client |
Bit 0 – BMODE Bit-Length Mode Select(1)
Value | Description |
---|---|
1 | SPIxTWIDTH setting applies to every byte: total bits sent is
SPIxTWIDTH*SPIxTCNT, end-of-packet occurs when SPIxTCNT =
0 |
0 | SPIxTWIDTH setting applies only to the last byte exchanged; total bits sent is SPIxTWIDTH + (SPIxTCNT*8) |