29.9.7 TUxyPR (16-bit)

Timer Period Register for 16-bit version of UTMR module.
Note:
  1. This register is double-buffered; effective PR value is loaded as defined by Timer Period Register.
  2. Data written to higher bytes is buffered; data written to LSB is also buffered and arms the effective PR value to be loaded at the next Reset or CLR event.
  3. Reading this register returns the data most-recently written, not necessarily the current PR setting.
  4. The individual bytes in this multibyte register can be accessed with the following register names:
    • TUxyPRH: Accesses the high byte TUxyPR[15:8]
    • TUxyPRL: Accesses the low byte TUxyPR[7:0]
Name: TU16yPR
Address: 0x3A5,0x3B3

Bit 15141312111098 
 PR[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 11111111 
Bit 76543210 
 PR[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 11111111 

Bits 15:0 – PR[15:0] Period value

The period of the timer.
Reset States: 
POR/BOR = 1111111111111111
All Other Resets = uuuuuuuuuuuuuuuu
This register is double-buffered; effective PR value is loaded as defined by Timer Period Register. Data written to higher bytes is buffered; data written to LSB is also buffered and arms the effective PR value to be loaded at the next Reset or CLR event. Reading this register returns the data most-recently written, not necessarily the current PR setting. The individual bytes in this multibyte register can be accessed with the following register names: TUxyPRH: Accesses the high byte TUxyPR[15:8] TUxyPRL: Accesses the low byte TUxyPR[7:0]