29.9.8 TUxyCLK

Clock Input Selector
Note:
  1. This register is not available when the module is chained and operated as a Secondary module.
Name: TUxyCLK

Bit 76543210 
    CLK[4:0] 
Access R/WR/WR/WR/WR/W 
Reset 00000 

Bits 4:0 – CLK[4:0] Clock Input Selector

Table 29-5. TUxyCLK Clock Input Selections
CLKClock Input
11111 - 11011Reserved
11010CLC8_OUT
11001CLC7_OUT
11000CLC6_OUT
10111CLC5_OUT
10110CLC4_OUT
10101CLC3_OUT
10100CLC2_OUT
10011CLC1_OUT
10010NCO1_OUT
10001PWM3S1P2_OUT
10000PWM3S1P1_OUT
01111PWM2S1P2_OUT
01110PWM2S1P1_OUT
01101PWM1S1P2_OUT
01100PWM1S1P1_OUT
01011CCP2_OUT
01010CCP1_OUT
01001CLKREF_OUT
01000EXTOSC
00111SOSC
00110MFINTOSC (31.25 kHz)
00101MFINTOSC (500 kHz)
00100LFINTOSC
00011HFINTOSC
00010FOSC
00001TUIN1PPS
00000TUIN0PPS
Reset States: 
POR/BOR = 00000
All Other Resets = uuuuu
This register is not available when the module is chained and operated as a Secondary module.