37.5.3 I2CxCON2

I2C Control Register 2
Name: I2CxCON2
Address: 0x294, 0x2AB

Bit 76543210 
 ACNTGCEN ABDSDAHT[1:0]BFRET[1:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 

Bit 7 – ACNT  Auto-Load I2C Count Register Enable

ValueDescription
1The first transmitted/received byte after the address is automatically loaded into the I2CxCNT register
0Auto-load of I2CxCNT is disabled

Bit 6 – GCEN  General Call Address Enable (used when MODE = 00x or MODE = 11x)

ValueDescription
1General Call Address (0x00) causes an address match event
0General Call addressing is disabled

Bit 4 – ABD Address Buffer Disable

ValueDescription
1Address buffers are disabled.

Received address is loaded into I2CxRXB, address to transmit is loaded into I2CxTXB.

0Address buffers are enabled.

Received address is loaded into I2CxADB0/I2CxADB1, address to transmit is loaded into I2CxADB0/I2CxADB1.

Bits 3:2 – SDAHT[1:0] SDA Hold Time Selection

ValueDescription
11No additional hold time on SDA after falling edge of SCL
10Minimum of 30 ns hold time on SDA after the falling SCL edge
01Minimum of 100 ns hold time on SDA after the falling SCL edge
00Minimum of 300 ns hold time on SDA after the falling SCL edge

Bits 1:0 – BFRET[1:0] Bus Free Time Selection

ValueBFREDR = 0BFREDR = 1
1164 baud-divided I2CxCLK pulses16 baud-divided I2CxCLK pulses
1032 baud-divided I2CxCLK pulses8 baud-divided I2CxCLK pulses
0116 baud-divided I2CxCLK pulses4 baud-divided I2CxCLK pulses
008 baud-divided I2CxCLK pulses2 baud-divided I2CxCLK pulses