37.5.10 I2CxCLK

I2C Clock Selection Register

Name:	I2CxCLK
Address:	0x29D, 0x2B4


Bit	7	6	5	4	3	2	1	0
				CLK[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0

Bits 4:0 – CLK[4:0] I2C Clock Selection

Table 37-6.
CLK	Selection
`11111 - 10100`	Reserved
`10011`	CLC8_out
`10010`	CLC7_out
`10001`	CLC6_out
`10000`	CLC5_out
`01111`	CLC4_out
`01110`	CLC3_out
`01101`	CLC2_out
`01100`	CLC1_out
`01011`	TU16B_OUT
`01010`	TU16A_OUT
`01001`	TMR6_Postscaler_OUT
`01000`	TMR4_Postscaler_OUT
`00111`	TMR2_Postscaler_OUT
`00110`	TMR0_OUT
`00101`	EXTOSC
`00100`	Clock Reference output
`00011`	MFINTOSC (500 kHz)
`00010`	HFINTOSC
`00001`	F_OSC
`00000`	F_OSC/4

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