11.13.30 PIR11

Peripheral Interrupt Request Register 11
Note:
  1. Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software must ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
  2. SPI2IF is a read-only bit. To clear the interrupt condition, all bits in the SPI2INTF register must be cleared.
  3. SPI2TXIF and SPI2RXIF are read-only bits and cannot be set/cleared by software.
Name: PIR11
Address: 0x4C1

Bit 76543210 
    VDDIO2RDYIFVDDIO2LVDIFSPI2IFSPI2TXIFSPI2RXIF 
Access RRRRR 
Reset 00000 

Bit 4 – VDDIO2RDYIF VDDIO2 Ready Interrupt Flag

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 3 – VDDIO2LVDIF VDDIO2 LVD Interrupt Flag

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 2 – SPI2IF  SPI2 Interrupt Flag(2)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 1 – SPI2TXIF  SPI2 Transmit Interrupt Flag(3)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 0 – SPI2RXIF  SPI2 Receive Interrupt Flag(3)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred
Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software must ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. SPI2IF is a read-only bit. To clear the interrupt condition, all bits in the SPI2INTF register must be cleared. SPI2TXIF and SPI2RXIF are read-only bits and cannot be set/cleared by software.