11.13.20 PIR1

Peripheral Interrupt Request Register 1

Note:

Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software must ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
The external interrupt GPIO pin is selected by the INTxPPS register.
I2C2EIF is a read-only bit. To clear the interrupt condition, all bits in the I2C2ERR register must be cleared.
I2C2IF is a read-only bit. To clear the interrupt condition, all bits in the I2C2PIR register must be cleared.
I2C2TXIF and I2C2RXIF are read-only bits. To clear the interrupt condition, the CLRBF bit in I2C2STAT1 must be set.

Name:	PIR1
Address:	0x4B7


Bit	7	6	5	4	3	2	1	0
	I2C2EIF	I2C2IF	I2C2TXIF	I2C2RXIF	ACTIF	ADIF	ADTIF	INT0IF
Access	R	R	R	R	R/W/HS	R/W/HS	R/W/HS	R/W/HS
Reset	0	0	0	0	0	0	0	0

Bit 7 – I2C2EIF I2C2 Error Interrupt Flag⁽³⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 6 – I2C2IF I2C2 Interrupt Flag⁽⁴⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 5 – I2C2TXIF I2C2 Transmit Interrupt Flag⁽⁵⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 4 – I2C2RXIF I2C2 Receive Interrupt Flag⁽⁵⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 3 – ACTIF Active Clock Tuning Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 2 – ADIF ADC Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 1 – ADTIF ADC Threshold Interrupt Flag

Value	Description
1	Interrupt event has not occurred
0	Interrupt has occurred

Bit 0 – INT0IF External Interrupt 0 Interrupt Flag⁽²⁾

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software must ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The external interrupt GPIO pin is selected by the INTxPPS register. I2C2EIF is a read-only bit. To clear the interrupt condition, all bits in the I2C2ERR register must be cleared. I2C2IF is a read-only bit. To clear the interrupt condition, all bits in the I2C2PIR register must be cleared. I2C2TXIF and I2C2RXIF are read-only bits. To clear the interrupt condition, the CLRBF bit in I2C2STAT1 must be set.