24.8.4 CLCnSEL0

Generic CLCn Data 1 Select Register
Name: CLCnSEL0
Address: 0x0D8

Bit 76543210 
   D1S[5:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset xxxxxx 

Bits 5:0 – D1S[5:0] CLCn Data1 Input Selection

Table 24-2. CLC Input Selection
DyS Input SourceDyS (cont.)Input Source (cont.)DyS (cont.)Input Source (cont.)
[0] 0000 0000CLCIN0PPS[22] 0001 0110TMR4[44] 0010 1100CLC6
[1] 0000 0001CLCIN1PPS[23] 0001 0111TMR6[45] 0010 1101CLC7
[2] 0000 0010CLCIN2PPS[24] 0001 1000CCP1[46] 0010 1110CLC8
[3] 0000 0011CLCIN3PPS[25] 0001 1001CCP2[47] 0010 1111U1TX
[4] 0000 0100CLCIN4PPS[26] 0001 1010PWM1S1P1_OUT[48] 0011 0000U2TX
[5] 0000 0101CLCIN5PPS[27] 0001 1011PWM1S1P2_OUT[49] 0011 0001SPI1_SDO
[6] 0000 0110CLCIN6PPS[28] 0001 1100PWM2S1P1_OUT[50] 0011 0010SPI1_SCK
[7] 0000 0111CLCIN7PPS[29] 0001 1101PWM2S1P2_OUT[51] 0011 0011SPI1_SS
[8] 0000 1000FOSC[30] 0001 1110PWM3S1P1_OUT[52] 0011 0100SPI2_SDO
[9] 0000 1001HFINTOSC(1)[31] 0001 1111PWM3S1P2_OUT[53] 0011 0101SPI2_SCK
[10] 0000 1010LFINTOSC(1)[32] 0010 0000NCO1[54] 0011 0110SPI2_SS
[11] 0000 1011MFINTOSC(1)[33] 0010 0001CMP1_OUT[55] 0011 0111I2C1_SCL
[12] 0000 1100MFINTOSC (31.25 kHz)(1)[34] 0010 0010CMP2_OUT[56] 0011 1000I2C1_SDA
[13] 0000 1101SFINTOSC (1 MHz)(1)[35] 0010 0011ZCD1[57] 0011 1001I2C2_SCL
[14] 0000 1110SOSC(1)[36] 0010 0100ZCD2[58] 0011 1010I2C2_SDA
[15] 0000 1111EXTOSC(1)[37] 0010 0101IOC[59] 0011 1011CWG1A
[16] 0001 0000ADCRC(1)[38] 0010 0110HLVD_OUT [60] 0011 1100CWG1B
[17] 0001 0001CLKR[39] 0010 0111CLC1[61] 0011 1101TU16A
[18] 0001 0010TMR0[40] 0010 1000CLC2[62] 0011 1110TU16B
[19] 0001 0011TMR1[41] 0010 1001CLC3[63] 0011 1111PORTW IOC
[20] 0001 0100TMR2[42] 0010 1010CLC4[64] 0100 0000-
[21] 0001 0101TMR3[43] 0010 1011CLC5[65] 0100 0001-
Note:
  1. Requests clock.
Reset States: 
POR/BOR = xxxxxx
All Other Resets = uuuuuu