22.2 PPS Inputs

Each digital peripheral has a dedicated PPS Peripheral Input Selection (xxxPPS) register with which the input pin to the peripheral is selected. Devices that have 20 leads or less (8/14/16/20) allow PPS routing to any I/O pin, while devices with 28 leads or more allow PPS routing to I/Os contained within two ports (see the table below).

Important: The notation “xxx” in the generic register name is a placeholder for the peripheral identifier. For example, xxx = T0CKI for the T0CKIPPS register.

Multiple peripherals can operate from the same source simultaneously. Port reads always return the pin level regardless of peripheral PPS selection. If a pin also has analog functions associated, the ANSEL bit for that pin must be cleared to enable the digital input buffer.

Table 22-1. PPS Input Selection Table
PeripheralPPS Input RegisterDefault Pin Selection at PORRegister Reset Value at PORAvailable Input Port
28-Pin Devices40-Pin Devices48-Pin Devices
Interrupt 0INT0PPSRB0‘b001 000AB—WAB———WAB————W
Interrupt 1INT1PPSRB1‘b001 001AB—WAB———W—B—D——W
Interrupt 2INT2PPSRB2‘b001 010AB—WAB———W—B———FW
Timer0 ClockT0CKIPPSRA4‘b000 100AB—WAB———WA————FW
Timer1 ClockT1CKIPPSRC0‘b010 000A—CWA—C——W——C—E—W
Timer1 GateT1GPPSRB5‘b001 101—BCW—BC——W—BC———W
Timer3 ClockT3CKIPPSRC0‘b010 000—BCW—BC——W——C—E—W
Timer3 GateT3GPPSRC0‘b010 000A—CWA—C——WA—C———W
Timer2 InputT2INPPSRC3‘b010 011A—CWA—C——WA—C———W
Timer4 InputT4INPPSRC5‘b010 101—BCW—BC——W—BC———W
Timer6 InputT6INPPSRB7‘b001 111—BCW—B—D—W—B—D——W
Universal Timer Input 0TUIN0PPSRC0‘b010 000A—CW——C—EW——C—E—W
Universal Timer Input 1TUIN1PPSRB5‘b001 101—BCW—BC——W—B———F—W
CCP1CCP1PPSRC2‘b010 010—BCW—BC——W——C——FW
CCP2CCP2PPSRC1‘b010 001—BCW—BC——W——C——FW
PWM Input 0PWMIN0PPSRC2‘b010 010—BCW—BC——W——C——FW
PWM Input 1PWMIN1PPSRC1‘b010 001—BCW—BC——W——C——FW
PWM1 External Reset SourcePWM1ERSPPSRC3‘b010 011A—CWA—C——WA—C— —W
PWM2 External Reset SourcePWM2ERSPPSRC5‘b010 101A—CWA—C——W——C—E—W
PWM3 External Reset SourcePWM3ERSPPSRB7‘b001 111—BCW—B—D—W—B—D——W
CWG1CWG1PPSRB0‘b001 000—BC——B—D———B—D———
CLCx Input 1CLCIN0PPSRA0‘b000 000A—CWA—C——WA—C———W
CLCx Input 2CLCIN1PPSRA1‘b000 001A—CWA—C——WA—C———W
CLCx Input 3CLCIN2PPSRB6‘b001 110—BCW—B—D—W—B—D——W
CLCx Input 4CLCIN3PPSRB7‘b001 111—BCW—B—D—W—B—D——W
CLCx Input 5CLCIN4PPSRA0‘b000 000A—CWA—C——WA—C———W
CLCx Input 6CLCIN5PPSRA1‘b000 001A—CWA—C——WA—C———W
CLCx Input 7CLCIN6PPSRB6‘b001 110—BCW—B—D—W—B—D——W
CLCx Input 8CLCIN7PPSRB7‘b001 111—BCW—B—D—W—B—D——W
ADC Conversion TriggerADACTPPSRB4‘b001 100—BCW—B—D—W—B—D——W
SPI1 ClockSPI1SCKPPSRC3‘b010 011—BCW—BC——W—BC———W
SPI1 DataSPI1SDIPPSRC4‘b010 100—BCW—BC——W—BC———W
SPI1 Client SelectSPI1SSPPSRA5‘b000 101A—CWA——D—WA——D——W
SPI2 ClockSPI2SCKPPSRB1‘b001 001—BCW—B—D—W—B—D——W
SPI2 DataSPI2SDIPPSRB2‘b001 010—BCW—B—D—W—B—D——W
SPI2 Client SelectSPI2SSPPSRB0‘b001 000—BCW—B—D—W—B—D——W
I2C1 ClockI2C1SCLPPS(1)RC3‘b010 011—BC——BC————BC————
I2C1 DataI2C1SDAPPS(1)RC4‘b010 100—BC——BC————BC————
I2C2 ClockI2C2SCLPPS(1)RB1‘b001 001—BC——B—D———B—D———
I2C2 DataI2C2SDAPPS(1)RB2‘b001 010—BC——B—D———B—D———
UART1 ReceiveU1RXPPSRC5‘b010 111—BCW—BC——W——C——FW
UART1 Clear to SendU1CTSPPSRC6‘b010 110—BC——BC—————C——F—
UART2 ReceiveU2RXPPSRB7‘b001 111—BCW—B—D—W—B—D——W
UART2 Clear to SendU2CTSPPSRB6‘b001 110—BC——B—D———B—D———
PORTW Input 0PORTWIN0PPSRB2‘b001 010AB———B—D———B—D———
PORTW Input 1PORTWIN1PPSRB0‘b001 000AB———B—D———B—D———
PORTW ClockPORTWCLKPPSRB1‘b001 001AB———B—D———B—D———
Note:
  1. Bidirectional pin. The corresponding output must select the same pin.