4.1 Multiplexed Signals


TQFP48/ VQFN48	PDIP40(4)	TQFP32/ VQFN32	SSOP28	Pin name^(1,2)	Special	ADC0	AC0	USARTn	SPI0	TWI0	TCA0	TCBn	EVSYS	CCL-LUTn
44	33	30	22	PA0	EXTCLK			0,TxD			0-WO0			0-IN0
45	34	31	23	PA1				0,RxD			0-WO1			0-IN1
46	35	32	24	PA2	TWI			0,XCK		SDA(MS)	0-WO2	0-WO	EVOUTA	0-IN2
47	36	1	25	PA3	TWI			0,XDIR		SCL(MS)	0-WO3	1-WO		0-OUT
48	37	2	26	PA4				0,TxD⁽³⁾	MOSI		0-WO4
1	38	3	27	PA5				0,RxD⁽³⁾	MISO		0-WO5
2	39	4	28	PA6				0,XCK⁽³⁾	SCK					0-OUT⁽³⁾
3	40	5	1	PA7	CLKOUT		OUT	0,XDIR⁽³⁾	SS				EVOUTA⁽³⁾
4				PB0				3,TxD			0-WO0⁽³⁾
5				PB1				3,RxD			0-WO1⁽³⁾
6				PB2				3,XCK			0-WO2⁽³⁾		EVOUTB
7				PB3				3,XDIR			0-WO3⁽³⁾
8				PB4				3,TxD⁽³⁾			0-WO4⁽³⁾	2-WO⁽³⁾
9				PB5				3,RxD⁽³⁾			0-WO5⁽³⁾	3-WO
10	1	6	2	PC0				1,TxD	MOSI⁽³⁾		0-WO0⁽³⁾	2-WO		1-IN0
11	2	7	3	PC1				1,RxD	MISO⁽³⁾		0-WO1⁽³⁾	3-WO⁽³⁾		1-IN1
12	3	8	4	PC2	TWI			1,XCK	SCK⁽³⁾	SDA(MS)⁽³⁾	0-WO2⁽³⁾		EVOUTC	1-IN2
13	4	9	5	PC3	TWI			1,XDIR	SS⁽³⁾	SCL(MS)⁽³⁾	0-WO3⁽³⁾			1-OUT
14	5			VDD
15	6			GND
16	7			PC4				1,TxD⁽³⁾			0-WO4⁽³⁾
17	8			PC5				1,RxD⁽³⁾			0-WO5⁽³⁾
18				PC6				1,XCK⁽³⁾						1-OUT⁽³⁾
19				PC7				1,XDIR⁽³⁾					EVOUTC⁽³⁾
20	9	10	6	PD0		AIN0					0-WO0⁽³⁾			2-IN0
21	10	11	7	PD1		AIN1	P3				0-WO1⁽³⁾			2-IN1
22	11	12	8	PD2		AIN2	P0				0-WO2⁽³⁾		EVOUTD	2-IN2
23	12	13	9	PD3		AIN3	N0				0-WO3⁽³⁾			2-OUT
24	13	14	10	PD4		AIN4	P1				0-WO4⁽³⁾
25	14	15	11	PD5		AIN5	N1				0-WO5⁽³⁾
26	15	16	12	PD6		AIN6	P2							2-OUT⁽³⁾
27	16	17	13	PD7	VREFA	AIN7	N2						EVOUTD⁽³⁾
28	17	18	14	AVDD
29	18	19	15	GND
30	19			PE0		AIN8			MOSI⁽³⁾		0-WO0⁽³⁾
31	20			PE1		AIN9			MISO⁽³⁾		0-WO1⁽³⁾
32	21			PE2		AIN10			SCK⁽³⁾		0-WO2⁽³⁾		EVOUTE
33	22			PE3		AIN11			SS⁽³⁾		0-WO3⁽³⁾
34	23	20	16	PF0	TOSC1			2,TxD			0-WO0⁽³⁾			3-IN0
35	24	21	17	PF1	TOSC2			2,RxD			0-WO1⁽³⁾			3-IN1
36	25	22		PF2	TWI	AIN12		2,XCK		SDA(S)⁽³⁾	0-WO2⁽³⁾		EVOUTF	3-IN2
37	26	23		PF3	TWI	AIN13		2,XDIR		SCL(S)⁽³⁾	0-WO3⁽³⁾			3-OUT
38	27	24		PF4		AIN14		2,TxD⁽³⁾			0-WO4⁽³⁾	0-WO⁽³⁾
39	28	25		PF5		AIN15		2,RxD⁽³⁾			0-WO5⁽³⁾	1-WO⁽³⁾
40	29	26	18	PF6	RESET			2,XCK⁽³⁾						3-OUT⁽³⁾
41	30	27	19	UPDI
42	31	28	20	VDD
43	32	29	21	GND

Note:

Pin names are of type Pxn, with x being the PORT instance (A,B,C, ...) and n the pin number. Notation for signals is PORTx_PINn. All pins can be used as event input.
All pins can be used for external interrupt, where pins Px2 and Px6 of each port have full asynchronous detection.
Alternate pin positions. For selecting the alternate positions, refer to the PORTMUX documentation.
The 40-pin version of the ATmega4809 is using the die of the 48-pin ATmega4809 but offers fewer connected pads. For this reason, the pins PB[5:0] and PC[7:6] must be disabled (INPUT_DISABLE) or enable pull-ups (PULLUPEN).

ATmega4808/4809

4.1 Multiplexed Signals