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ATmega4808/4809 Data Sheet ATmega4808/4809
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ATmega4808
ATmega4809
Introduction
megaAVR® 0-series Overview
1
Memory Overview
2
Peripheral Overview
Features
1
Silicon Errata and Data Sheet Clarification Document
2
Block Diagram
3
Pinout
3.1
28-Pin SSOP
3.2
32-Pin VQFN/TQFP
3.3
40-Pin PDIP
3.4
48-Pin VQFN/TQFP
4
I/O Multiplexing and Considerations
4.1
Multiplexed Signals
5
Conventions
5.1
Numerical Notation
5.2
Memory Size and Type
5.3
Frequency and Time
5.4
Registers and Bits
5.5
ADC Parameter Definitions
6
AVR® CPU
6.1
Features
6.2
Overview
6.3
Architecture
6.4
Arithmetic Logic Unit (ALU)
6.5
Functional Description
6.6
Register Summary
6.7
Register Description
7
Memories
7.1
Overview
7.2
Memory Map
7.3
In-System Reprogrammable Flash Program Memory
7.4
SRAM Data Memory
7.5
EEPROM Data Memory
7.6
User Row (USERROW)
7.7
Signature Row (SIGROW)
7.8
Fuses (FUSE)
7.9
Memory Section Access from CPU and UPDI on Locked Device
7.10
I/O Memory
8
Peripherals and Architecture
8.1
Peripheral Module Address Map
8.2
Interrupt Vector Mapping
8.3
SYSCFG - System Configuration
9
NVMCTRL - Nonvolatile Memory Controller
9.1
Features
9.2
Overview
9.3
Functional Description
9.4
Register Summary
9.5
Register Description
10
CLKCTRL - Clock Controller
10.1
Features
10.2
Overview
10.3
Functional Description
10.4
Register Summary
10.5
Register Description
11
SLPCTRL - Sleep Controller
11.1
Features
11.2
Overview
11.3
Functional Description
11.4
Register Summary
11.5
Register Description
12
RSTCTRL - Reset Controller
12.1
Features
12.2
Overview
12.3
Functional Description
12.4
Register Summary
12.5
Register Description
13
CPUINT - CPU Interrupt Controller
13.1
Features
13.2
Overview
13.3
Functional Description
13.4
Register Summary
13.5
Register Description
14
EVSYS - Event System
14.1
Features
14.2
Overview
14.3
Functional Description
14.4
Register Summary
14.5
Register Description
15
PORTMUX - Port Multiplexer
15.1
Overview
15.2
Register Summary - PORTMUX
15.3
Register Description
16
PORT - I/O Pin Configuration
16.1
Features
16.2
Overview
16.3
Functional Description
16.4
Register Summary - PORTx
16.5
Register Description - PORTx
16.6
Register Summary - VPORTx
16.7
Register Description - VPORTx
17
BOD - Brown-out Detector
17.1
Features
17.2
Overview
17.3
Functional Description
17.4
Register Summary
17.5
Register Description
18
VREF - Voltage Reference
18.1
Features
18.2
Overview
18.3
Functional Description
18.4
Register Summary - VREF
18.5
Register Description
19
WDT - Watchdog Timer
19.1
Features
19.2
Overview
19.3
Functional Description
19.4
Register Summary - WDT
19.5
Register Description
20
TCA - 16-bit Timer/Counter Type A
20.1
Features
20.2
Overview
20.3
Functional Description
20.4
Register Summary - Normal Mode
20.5
Register Description - Normal Mode
20.6
Register Summary - Split Mode
20.7
Register Description - Split Mode
21
TCB - 16-Bit Timer/Counter Type B
21.1
Features
21.2
Overview
21.3
Functional Description
21.4
Register Summary
21.5
Register Description
22
RTC - Real-Time Counter
22.1
Features
22.2
Overview
22.3
Clocks
22.4
RTC Functional Description
22.5
PIT Functional Description
22.6
Crystal Error Correction
22.7
Events
22.8
Interrupts
22.9
Sleep Mode Operation
22.10
Synchronization
22.11
Debug Operation
22.12
Register Summary
22.13
Register Description
23
USART - Universal Synchronous and Asynchronous Receiver and Transmitter
23.1
Features
23.2
Overview
23.3
Functional Description
23.4
Register Summary
23.5
Register Description
24
SPI - Serial Peripheral Interface
24.1
Features
24.2
Overview
24.3
Functional Description
24.4
Register Summary
24.5
Register Description
25
TWI - Two-Wire Interface
25.1
Features
25.2
Overview
25.3
Functional Description
25.4
Register Summary
25.5
Register Description
26
CRCSCAN - Cyclic Redundancy Check Memory Scan
26.1
Features
26.2
Overview
26.3
Functional Description
26.4
Register Summary - CRCSCAN
26.5
Register Description
27
CCL - Configurable Custom Logic
27.1
Features
27.2
Overview
27.3
Functional Description
27.4
Register Summary
27.5
Register Description
28
AC - Analog Comparator
28.1
Features
28.2
Overview
28.3
Functional Description
28.4
Register Summary
28.5
Register Description
29
ADC - Analog-to-Digital Converter
29.1
Features
29.2
Overview
29.3
Functional Description
29.4
Register Summary - ADCn
29.5
Register Description
30
UPDI - Unified Program and Debug Interface
30.1
Features
30.2
Overview
30.3
Functional Description
30.4
Register Summary
30.5
Register Description
31
Instruction Set Summary
32
Electrical Characteristics
32.1
Disclaimer
32.2
Absolute Maximum Ratings
32.3
General Operating Ratings
32.4
Power Considerations
32.5
Power Consumption
32.6
Wake-Up Time
32.7
Peripherals Power Consumption
32.8
BOD and POR Characteristics
32.9
External Reset Characteristics
32.10
Oscillators and Clocks
32.11
I/O Pin Characteristics
32.12
USART
32.13
SPI
32.14
TWI
32.15
VREF
32.16
ADC
32.17
TEMPSENSE
32.18
AC
32.19
UPDI
32.20
Programming Time
33
Typical Characteristics
33.1
Power Consumption
33.2
GPIO
33.3
VREF Characteristics
33.4
BOD Characteristics
33.5
ADC Characteristics
33.6
TEMPSENSE Characteristics
33.7
AC Characteristics
33.8
OSC20M Characteristics
33.9
OSCULP32K Characteristics
34
Ordering Information
35
Package Drawings
35.1
Package Marking Information
35.2
Online Package Drawings
35.3
28-Pin SSOP
35.4
32-Pin TQFP
35.5
32-Pin VQFN
35.6
32-Pin VQFN Wettable Flanks
35.7
40-Pin PDIP
35.8
48-Pin TQFP
35.9
48-Pin VQFN
35.10
48-Pin VQFN Wettable Flanks
36
Data Sheet Revision History
36.1
Rev. C - 02/2021
36.2
Rev. B - 06/2020
36.3
Rev.A - 01/2020
36.4
Appendix - Obsolete Revision History
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