| Entire Document |
- Terminology
update:
- The SPI
and TWI standards use the terminology "Master" and
"Slave". The equivalent Microchip terminology used in
this document is "Host" and "Client" respectively.
- Editorial updates
throughout the document
|
| Table of Contents |
- Removed the
peripheral name in the title under the peripheral Register
Summary and Register Description sections
- The Crystal
Error Correction section is added
|
| megaAVR® 0-series Overview |
- Updated the megaAVR® Device Designations figure
|
| Features |
- Speed grade
range upper limit is changed from -40°C to +105°C. Speed
grade range added for Automotive part
|
| Pinout |
RESET text added for pin PF6 |
| AVR® CPU |
- The Arithmetic
Logic Unit (ALU) section is updated to differentiate between
register and working register
- Program Flow
section is updated to clarify changes in the program flow
- The Stack and
Stack Pointer section is updated:
- Clarify the pushing and popping of data onto the
stack
- The reference to EICAL instruction removed
- The Register File
section is updated to clarify instruction access to the register
file
- The X-, Y-, and
Z-Register section is updated to differentiate between register
and working register and certify the different addressing
modes
- The Status
Register description is updated to be in line with the AVR
Instruction Set description
- The Accessing
16-Bit Registers section is added
|
| Peripherals and Architecture |
- The Interrupt
vector Mapping table is updated :
- Added Description and Peripherals Source
names columns
- The
Vector Address changed to Program address
(word)
|
| NVMCTRL - Nonvolatile Memory Controller |
- Updated the
NVMCTRL Block Diagram for better understanding of the
NVMCTRL peripheral
- Improved the
Set Up Flash Sections table description of the
boot section lock and application code
sections
- Added a section
detailing the write access after Power-on Reset
- Added the
NVMCTRL.CTRLB to registers under Configuration Change
Protection
|
| CLKCTRL - Clock Controller |
- Corrected the
Block Diagram by removing the TCD timer which
is not present on this device
- Updated the
MCLKCTRLB, PDIV bit field description (table changed)
|
| SLPCTRL - Sleep Controller |
- In the Sleep Mode Activity Overview for Peripherals
table:
- Removed
column Clock and Group
- Updated notes below the table
- Added separate
tables Sleep Mode Activity for Clock Source and Sleep
Mode Activity Wake-up Sources
|
| RSTCTRL - Reset Controller |
- Updated
Features to improve the readability of Reset
sources grouping Power Supply Reset Sources and
User Reset Sources
- Improved the
working principle of the different reset sources and inclusion
of timing diagrams in Functional Description under
Initialization section
- In the Logic
Domains Affected by Various Resets table removed
columns:
- TCD Pin Override Functionality Available
- Reset of TCD Pin Override Settings
- Reset of BOD configuration
- Clarified the behavior of the flags in the Reset Flag (RSTFR)
register after a POR has occurred
- Updated the
description in the Power-on Reset (POR) section
|
| CPUINT - CPU Interrupt Controller |
- Added a table to
improve the description, and moved relevant text below figures,
in the Interrupt Response Time section
- In the
High-Priority Interrupt section: Clarified that
priority level 1 will interrupt priority level 0 interrupts
- Added the
Debug Operation section
- Corrected the
terminology from number to address in the Interrupt Vector with
Priority Level 1 register description
|
| EVSYS - Event System |
- Improved the
Block Diagram figure by adding EVOUTx
- In the Event
Generators section, improved readability by adding the
Properties of Generated Events and the Event
Generators tables.
- Added information
on event user synchronization
|
| PORT - I/O Pin Configuration |
- Improved the
Overview text and the Block Diagram
- Updated
Functional Description:
- Added
optional initialization steps
- Moved Pin
n Control offset from Basic Functions to Pin
Configuration
- Clarified
that the pull-up is disabled when the output driver is
enabled
- Moved
interrupt settings considerations from the Pin
Configuration to the Interrupt
section
- Updated
the Asynchronous Sensing Pin Properties
section
- Updated
the Events section per AVR best practice
- Added the
Debug Operation section per AVR best
practice
- Updated the
Registers Description per AVR best practice
|
| WDT - Watchdog Timer |
- Improved the
Block Diagram
- Corrected the
oscillator frequency from 1 kHz to 1.024 kHz, and 32 kHz to
32.768 kHz
- In the
Control A register description in the Window
bit field table, the precision of the values have been
corrected
|
| TCA - 16-bit Timer/Counter Type A |
- Clarifications
added
- For
single-slope PWM generation, counting from TOP to BOTTOM
is not supported
- Dual-slope PWM results in approx. half the maximum
operation frequency compared to single-slope PWM
operation, due to twice the number of timer increments
per period
- Added timing diagram for split mode
- Event
actions with level input detection work reliably only if
the event frequency is lower than the timer’s
frequency
- (H/L)CMPnOV bits in CTRLC in normal and split mode:
When the output is connected to the pad, overriding
these bits requires the CMPnEN bits in the TCAn.CTRLB
register to be enabled. The CMPnEN bit is bypassed when
the output is connected to the CCL.
- LUPD bit
in CTRLESET/CLR: LUPD does not prevent an update issued
by CTRLE.CMD
- For
operation modes with update condition on BOTTOM and
compare interrupt enabled:
- If CMPn=0, an interrupt will be given together
with the update at BOTTOM
- If CMPnBUF=0, an interrupt will be given the next
time the counter reaches BOTTOM
|
| TCB - 16-bit Timer/Counter Type B |
- The
Initialization section is updated to include an
optional step to enable waveform output on a pin
- Time-Out Check
Mode_ Input Capture on Event Mode, Input Capture Frequency
Measurement Mode, Input Capture Pulse-Width Measurement Mode,
Input Capture Frequency and Pulse-Width Measurement Mode,
Single-Shot Mode sections explanation about TCB as event user
added
- In the
Single-Shot Mode section, the EDGE bit explanation is
corrected
- In the 8-Bit
PWM Mode section, the explanation of duty cycle and
period is corrected
- In the
Output section, the explanation of the CCMPEN bit is
added
- In the
Events section, the reference to the OVF event and
the COUNT event user are removed
- The Control B
register description is updated:
- The
CCMPINIT bit has no effect in Single-Shot and 8-bit PWM
mode
- Improved
description of the CCMPEN bit
- The Event Control
register description: The EDGE bit explanation is corrected
- The Temporary
Value register description is improved
- The
Capture/Compare register description explanation of the duty
cycle and period is corrected
|
| RTC - Real-Time Counter |
- Restructured the
Events Generators in RTC table:
- Added a
table for the Interrupt Control and the
Periodic Interrupt Timer Control A registers
- Added the
Feature Crystal Error Correction and related
text
- Added the
Frequency Error Correction bit in the CTRLA
register
- Added the
Crystal Frequency Calibration register
|
| USART - Universal Synchronous and Asynchronous Receiver and
Transmitter |
- In the
Overview section:
- single
- write is changed to two level -
write
- In the
Feature list and the IRCOM TXPLCTRL register,
system clock is change to peripheral
clock
- Changed the Block
diagram text
- Added information about the TX Buffer register
- Restructured the
Data Transmission and the Data Reception
sections
- Auto Baud
section text regarding tolerance configuration is added
- Register text
restructure and bit fields tables added:
- Receiver
Data Register Low Byte, Receiver Data Register High Byte
register, and USART Status
- USART
Status register table added for the configuration of the
bit field WFB
- Control
A, Control B register table added for bit field
configuration
- Control D
register text was restructured and table values
regarding tolerance are updated
- IrDA
Control register added table
- Register name
changed from Control C - Asynchronous Mode to Control
C - Normal Mode
|
| SPI - Serial Peripheral Interface |
- First Receive
Buffer and Second Receive Buffer registers now referred to as
Receive Data Register and Receive Data Register
|
| TWI - Two-Wire Interface |
- Updated the
Features section terminology
- Added the
Debug Operation section
- Clarifications
and corrections
- Description of Bus Error (BUSERR) in MSTATUS and
SSTATUS registers
- Description of Address Packet Flag Activation of
Read/Write Interrupt Flags (WIF/RIF) in MSTATUS
register
- Description of Data and Address or Stop Interrupt Flags
(DIF/APIF) in SSTATUS register
- Behavior
of the Acknowledge Action (ACKACT) bit in MCTRLB,
MDATA, SCTRLB registers
- The
Clock Generation section is expanded to
ensure correct low times for SCL in Fm+ mode
|
| CRCSCAN - Cyclic Redundancy Check Memory Scan |
- Improved
description of CRC scan in ENABLE bit in the Control A
(CRCSCAN.CTRLA) register, and the OK bit in the Status
(CRCSCAN.STATUS) register
- Added missing CRC
Flash Access Mode (MODE) bit field in the Control B
(CRCSCAN.CTRLB) register
|
| CCL - Configurable Custom Logic |
- LUTn-IN[] has
been renamed to LUTn-TRUTHSEL[] to better reflect its
functionality
- The Truth
Table Logic section is rewritten for clarity and an
example is added
- The Event
Input Selection (EVENTx) section reference to a wrong
register is corrected
- The CTRLA
register description is rewritten for clarity
- The TRUTHn
register description is updated to include a truth table
|
| AC - Analog Comparator |
- The Input
Sources section: Fixed typo from MUXTRLA to
MUXCTRLA
- The Power
Modes section: Fixed bug from MODE to LPMODE
- The Internal
Inputs section: Fixed typo from DAC to AC
- Restructured the
text for the Events section
- Added a title to
the bit field table INTMODE in Control A register
- Restructured the
text for the INVERT bit field in the MUX Control register
- Restructured the
text for the DAC Voltage Reference register
|
| ADC - Analog-to-Digital Converter |
- Added the
Definitions section to define terms such as Offset or
Gain Error, Integral Non-Linearity, and Differential
Non-Linearity among others
- Correction of the
bit field name from WCOMP to WCMP, in both INTCTRL and INTFLAG
registers
|
| UPDI - Unified Program and Debug Interface |
- Reorganized the
BREAK Character section into BREAK and SYNCH with some more
details
- In the ASI
Control A register added the missing value,
0x00 (32 MHz UPDI Clock), to the UPDI Clock
Select bit field - In the Status A
register, the UPDI Revision bit field Access Reset is corrected
from
0x01 to 0x03
|
| Electrical Characteristics |
- General Operating
Ratings
- Clarified ranges in the Maximum Frequency vs. VDD
figures
- Added
Maximum Frequency vs. VDD figure for
automotive range parts
- Power Consumption
- Clarified
clock source for the Active/Idle Supply vs.
Frequency plots
- Added a
Max. 25°C column in the Power Consumption in
Power-Down, Standby and Reset Mode table
- External Reset
Characteristics
- Number
for tMIN_RST max limit updated
- TWI
- Updated
the TWI - Specifications table with typical
numbers for tHD;STA, tSU;STA, tSU;STD and tBUF
- Added
SDA Hold Time table
- TEMPSENSE
Characteristics
- Added the
TEMPSENSE Characteristics section
- UPDI
- Updated
the UPDI Max. Bit Rates vs. VDD table
|
| Package Drawings | Section Package Marking Information added |
