29.3.2.2 Clock Generation
The ADC requires an input clock frequency between 50 kHz and 1.5 MHz for maximum resolution. If a lower resolution than ten bits is selected, the input clock frequency to the ADC can be higher than 1.5 MHz to get a higher sample rate.
The ADC module contains a prescaler which generates the ADC
clock (CLK_ADC) from any CPU clock (CLK_PER) above 100 kHz. The prescaling is selected by
writing to the Prescaler (PRESC) bits in the Control C (ADCn.CTRLC) register. The prescaler
starts counting from the moment the ADC is switched on by writing a ‘1’ to
the ENABLE bit in ADCn.CTRLA. The prescaler keeps running as long as the ENABLE bit is
‘1’. The prescaler counter is reset to zero when the ENABLE bit is
‘0’.
When initiating a conversion by writing a
‘1’ to the Start Conversion (STCONV) bit in the Command (ADCn.COMMAND)
register or from an event, the conversion starts at the following rising edge of the
CLK_ADC clock cycle. The prescaler is kept reset as long as there is no ongoing conversion.
This assures a fixed delay from the trigger to the actual start of a conversion in CLK_PER
cycles, as follows:
