9.5.4 Interrupt Control
| Name: | INTCTRL |
| Offset: | 0x03 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EEREADY | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bit 0 – EEREADY EEPROM Ready Interrupt
Writing a ‘1’ to this bit enables the interrupt,
which indicates that the EEPROM is ready for new write/erase operations.
This is a level interrupt that will be triggered only when the EEREADY flag in
the INTFLAGS register is set to ‘0’. Thus, the interrupt must
not be enabled before triggering an NVM command, as the EEREADY flag will not be
set before the NVM command is issued. The interrupt may be disabled in the
interrupt handler.