30.3.2.1 UPDI Enable

The dedicated UPDI pad is configured as an input with pull-up.When the pull-up is detected by a connected debugger, the UPDI enable sequence, as depicted below, is started.

Figure 30-4. UPDI Enable Sequence
Table 30-4. Timing in the Figure
Timing LabelMax.Min.
tRES200 µs10 µs
tUPDI200 µs10 µs
tDeb01 µs200 ns
tDebZ14 ms200 µs

When the pull-up is detected, the debugger initiates the enable sequence by driving the line low for a duration of tDeb0.

The negative edge is detected by the UPDI, which starts the UPDI clock. The UPDI will continue to drive the line low until the clock is stable and ready for the UPDI to use. The duration of tUPDI will vary, depending on the status of the oscillator when the UPDI is enabled. After this duration, the data line will be released by the UPDI and pulled high.

When the debugger detects that the line is high, the initial SYNCH character (0x55) must be transmitted to synchronize the UPDI communication data rate. If the Start bit of the SYNCH character is not sent within maximum tDebZ, the UPDI will disable itself, and the UPDI enabling sequence must be re-initiated. The UPDI is disabled if the timing is violated to avoid the UPDI being enabled unintentionally.

After successful SYNCH character transmission, the first instruction frame can be transmitted.