10.5.2 Main Clock Control B
| Name: | MCLKCTRLB |
| Offset: | 0x01 |
| Reset: | 0x11 |
| Property: | Configuration Change Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PDIV[3:0] | PEN | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 1 | 0 | 0 | 0 | 1 | ||||
Bits 4:1 – PDIV[3:0] Prescaler Division
If the Prescaler Enable (PEN) bit is written to ‘1’,
these bits define the division ratio of the main clock prescaler.
These bits can be written during run-time to vary the clock frequency of the system to suit the application requirements.
The user software must ensure a correct configuration of the input frequency (CLK_MAIN) and prescaler settings, so that the resulting frequency of CLK_PER never exceeds the allowed maximum (see Electrical Characteristics).
| Value | Name | Description |
|---|---|---|
| 0x0 | DIV2 | CLK_MAIN divided by 2 |
| 0x1 | DIV4 | CLK_MAIN divided by 4 |
| 0x2 | DIV8 | CLK_MAIN divided by 8 |
| 0x3 | DIV16 | CLK_MAIN divided by 16 |
| 0x4 | DIV32 | CLK_MAIN divided by 32 |
| 0x5 | DIV64 | CLK_MAIN divided by 64 |
| 0x6-0x7 | - | Reserved |
| 0x8 | DIV6 | CLK_MAIN divided by 6 |
| 0x9 | DIV10 | CLK_MAIN divided by 10 |
| 0xA | DIV12 | CLK_MAIN divided by 12 |
| 0xB | DIV24 | CLK_MAIN divided by 24 |
| 0xC | DIV48 | CLK_MAIN divided by 48 |
| other | - | Reserved |
Bit 0 – PEN Prescaler Enable
This bit must be written to ‘1’ to enable the
prescaler. When enabled, the division ratio is selected by the PDIV bit
field.
When this bit is written to ‘0’, the main clock will
pass through undivided (CLK_PER = CLK_MAIN), regardless of the value of
PDIV.