5 Example: Totem Pole PFC

For this example, the dsPIC33C Totem Pole Demonstration Application development board was used for plant measurement. This development board is designed for rapid prototyping and code development using Microchip’s dsPIC33C and Silicon Carbine (SiC FET) devices.

The parameters considered for this measurement include an inductance (L) of 340 µH, a capacitance (C_O) of 3.4 mF, an input voltage (V_IN) of 30V, an output voltage (V_O) of 47V and an output current (I_O) of 5A.

To determine the pole location in the BODE plot for the Totem Pole Power Factor Correction (PFC) circuit, the following formula is used:

$f_o=\frac{V_{IN}}{V_{OUT}\times 2\pi \sqrt{LC}}$

Substituting the given values into the equation:

$f_o=\frac{30V}{47V\times 2\pi \sqrt{\left(340uH\right)\times \left(3.4mF\right)}}=94.34Hz$

A 40 dB/decade slope in the Bode plot indicates that the system has a double pole, with each contributing to the overall rate of gain decrease.