8.4.6.2 Updating the QSPI Configuration
Once written in the registers, the configuration must be synchronized with the QSPI core.
At any time, the QSPI Controller core configuration can be updated by writing the QSPI_CR.UPDCFG bit to 1. This will update the QSPI core with the current register configuration. Note that QSPI_SR.SYNCBSY must be 0 before writing QSPI_CR.UPDCFG.
The configuration registers that require synchronization (writing QSPI_CR.UPDCFG to 1) with the QSPI Controller core are:
- QSPI Mode Register(1)
- QSPI Serial Clock Register
- QSPI Instruction Address Register
- QSPI Write Instruction Code Register
- QSPI Read Instruction Code Register
- QSPI Scrambling Mode Register
- QSPI Scrambling Key Register
- QSPI Refresh Register
- QSPI Write Access Counter Register
- QSPI Instruction Frame Register
Note:
- TAMPCLR in the Mode register (QSPI_MR) does not require synchronization with the QSPI core.