5.8.6.6 Parallel Front End (PFE) Module
The Parallel Front End module performs data resampling across clock domain boundary. It includes a CCIR656 decoder used to convert a standard ITU-R BT.656 stream to 24-bit digital video. It also generates pixels, syncs flags and valid signals to the main video pipeline. It ouputs field, video and synchronization signals. The PFE can optionally crop and limit the incoming pixel stream to a predefined horizontal and vertical value. By default, the PFE only relies on the input horizontal and vertical references to sample the incoming pixel stream. A pixel is sampled if, and only if, the vertical and horizontal synchronizations are valid and a pixel clock edge is detected. ISC_PFE_CFG0.BPS shows the number of bits per sample.
When operating with a parallel interface, the PFE module outputs a 12-bit data on the vp_data[11:0] bus, and asserts the vp_valid signal when the data can be sampled.
| PFE vp_data Mapping | Raw Bayer 12-bit | Raw Bayer 10-bit | YUV422 8-bit | YUV422 10-bit | Mono 12-bit |
|---|---|---|---|---|---|
| vp_data[39:12] | – | – | – | – | – |
| vp_data[11] | RGGB[11] | RGGB[9] | YC422[7] | YC422[9] | Y[11] |
| vp_data[10] | RGGB[10] | RGGB[8] | YC422[6] | YC422[8] | Y[10] |
| vp_data[9] | RGGB[9] | RGGB[7] | YC422[5] | YC422[7] | Y[9] |
| vp_data[8] | RGGB[8] | RGGB[6] | YC422[4] | YC422[6] | Y[8] |
| vp_data[7] | RGGB[7] | RGGB[5] | YC422[3] | YC422[5] | Y[7] |
| vp_data[6] | RGGB[6] | RGGB[4] | YC422[2] | YC422[4] | Y[6] |
| vp_data[5] | RGGB[5] | RGGB[3] | YC422[1] | YC422[3] | Y[5] |
| vp_data[4] | RGGB[4] | RGGB[2] | YC422[0] | YC422[2] | Y[4] |
| vp_data[3] | RGGB[3] | RGGB[1] | YC422[7] or 0 | YC422[1] | Y[3] |
| vp_data[2] | RGGB[2] | RGGB[0] | YC422[6] or 0 | YC422[0] | Y[2] |
| vp_data[1] | RGGB[1] | RGGB[9] or 0 | YC422[5] or 0 | YC422[9] or 0 | Y[1] |
| vp_data[0] | RGGB[0] | RGGB[8] or 0 | YC422[4] or 0 | YC422[8] or 0 | Y[0] |
When operating with MIPI RGB or YUV formats, the PFE module copies up to 40-bit data from isc_data[39:0] bus on the vp_data[39:0] bus, and asserts the vp_valid signal when the data can be sampled.
The PFE module also includes logic to synchronize capture request with the incoming pixel stream. Two operating modes are available: Single Shot and Continuous Acquisition. When ISC_PFE_CFG0.CONT is cleared, the ISC transfers a single image to memory,
When Continuous Acquisition mode is activated (ISC_PFE_CFG0.CONT is set), the data transfer terminates when either a DMA end of list is reached, a software disable is performed or a software reset is activated. ISC_INTSR.DDONE is set at the end of the DMA data transfer.
The linked list DMA transfer is terminated when an item of the list is programmed with ISC_DCTRL.DE cleared or when ISC_DNDA.NDA is equal to zero. This configuration also clears ISC_CTRLSR.CAPTURE and sets the ISC_INTSR.LDONE interrupt flag.
The linked list DMA transfer starts if ISC_DCTRL.DE is set and if ISC_DNDA.NDA is different from zero.