8.8.6.3.1 Initialization

Before enabling the output channel, this channel must have been configured by the software application:

• Configuration of the clock generator if DIVA and DIVB are required
• Selection of the clock for each channel (PWM_CMRx.CPRE)
• Configuration of the waveform alignment for each channel (PWM_CMRx.CALG)
• Configuration of the period for each channel (PWM_CPRDx.CPRD). Writing in PWM_CPRDx is possible while the channel is disabled. After validation of the channel, the user must use the Channel Update register (PWM_CUPDx) to update PWM_CPRDx as explained below.
• Configuration of the duty cycle for each channel (PWM_CDTYx.CDTY). Writing in PWM_CDTYx is possible while the channel is disabled. After validation of the channel, the user must use PWM_CUPDx to update PWM_CDTYx as explained below.
• Configuration of the output waveform polarity for each channel (PWM_CMRx.CPOL)
• Enable Interrupts (set CHIDx in the Interrupt Enable register (PWM_IER))
• Enable the PWM channel (set CHIDx in the Enable register (PWM_ENA))

It is possible to synchronize different channels by enabling them at the same time by means of simultaneously setting several CHIDx bits in PWM_ENA.

• In such a situation, all channels may have the same clock selector configuration and the same period specified.