10.1.3 Recommended Operating Conditions

Table 10-3. Recommended Operating Conditions on Power Supply Inputs
Power Input	Parameters	Conditions	Min	Max	Unit
VDDIN33	VDDOUT25 regulator input, USB interface I/O lines and Main crystal oscillator power supply⁽¹⁾	–	3.00	3.60	V
VDDANA	VDDANA I/O lines, A/D Converter and OTP memory power supply⁽¹⁾	–	3.00	3.60	V
VDDCORE	Core logic (processor, peripherals, memories, UTMI logic, etc.) power supply ⁽²⁾	f_CPU ≤ 600 MHz, f_MCK ≤ 200 MHz f_CPU ≤ 800 MHz, f_MCK ≤ 266 MHz	1.03 1.12	1.21 1.21	V
VDDIOM	SDRAM I/O lines power supply	DDR2-SDRAM DDR3-SDRAM DDR3L-SDRAM	1.70 1.425 1.283	1.90 1.575 1.450	V
VDDNF	NAND Flash I/O lines power supply⁽³⁾	–	1.70	3.60	V
VDDIOP0	VDDIOP0 I/O lines power supply⁽³⁾	–	1.70	3.60	V
VDDIOP1	VDDIOP1 I/O lines power supply⁽³⁾	–	1.70	3.60	V
VDDIOP2	VDDIOP2 I/O lines power supply⁽³⁾	–	1.70	3.60	V
VDDQSPI	VDDQSPI I/O lines power supply⁽³⁾	–	1.70	3.60	V
VDDLVDS	LVDS PHY and VDDLVDS I/O lines power supply⁽³⁾⁽⁴⁾	–	1.70	3.60	V
VDDMIPI	MIPI PHY and I/O lines power supply⁽⁵⁾	–	2.25	2.75	V
VDDBU	Backup domain power supply	–	1.6	3.60	V
t_{R_VDD}	Power supply slope at power-up	–	0.2	20	mV/µs
t_{F_VDD}	Power supply slope at power-down	–	–20	–1⁽⁶⁾	mV/µs

Note:

VDDANA and VDDIN33 are powered from one single source: V(VDDANA,VDDIN33) ≤ ±50mV.
For device lifetime estimation as a function of VDDCORE and temperature, refer to the application note “SAM9X7 Series Product Lifetime Estimation” (AN5531), available on www.microchip.com.
Supply range restrictions apply when using the digital peripheral timing characteristics. See I/O Characteristics.
When the LVDS PHY is used, VDDLVDS must be connected to VDDOUT25.
VDDMIPI must be connected to VDDOUT25.
For VDDBU, this value is 0 mV/µs.

Table 10-4. Recommended Operating Conditions on Input Pins⁽¹⁾
Symbol	Parameters	Conditions	Min	Max	Unit
V_IN	Input line voltage range on inputs⁽²⁾⁽³⁾	–	-0.3	V_DD+0.3	V
I_IN	DC current injection on input ⁽⁴⁾⁽⁵⁾	–	–	±0.2	mA
I_{TOT_INJ}	Total current injection per power rail or ground rail ⁽⁶⁾	–	–	±2	mA

Note:

In this table, VDD refers to the voltage of the associated power rail of the I/O line, as defined in the Pin Description table. Ex: for PA2, VDD refers to VDDIOP0.
Input voltages V_IN ≤ 0V or V_IN ≥ VDD lead to negative or positive current injection on inputs.
For analog inputs (PA[31:24]), input voltages V_IN ≥ min(V_DDANA, V_ADVREFP) lead to saturated A/D conversion to 0xFFF.
Current injection on A/D converter analog inputs (PA[31:24]) can degrade the analog performance of the corresponding channel or the analog performance of other analog channels.
High frequency current injection must be limited to avoid propagating high frequency signals to internal sensitive analog circuits (oscillators, regulators, etc.). One common use case of high frequency current injection occurs when a digital input pin suffers overshoots and/or undershoots from a poorly adapted transmission line (PCB trace with signal reflections, for example). These cases should be cured by appropriate source series resistor termination. Special attention must be paid to high speed interfaces (Gigabit Ethernet MAC I/F, SD card or e.MMC I/F, QSPI I/F, etc.).
Corresponds to the sum of the positive currents into one power rail and respectively to the sum of the negative currents into one ground rail, as defined in the Pin Description table.

Table 10-5. Recommended Operating Conditions on Internal Clocks
Symbol	Parameters	Conditions	Min	Max	Unit
f_{CPU_CLK}	Processor clock (CPU_CLK) frequency	VDDCORE ≥ 1.14V	–	800	MHz
f_{CPU_CLK}	Processor clock (CPU_CLK) frequency	VDDCORE ≥ 1.04V	–	600	MHz
f_MCK	Main system bus clock (MCK) frequency	VDDCORE ≥ 1.14V	–	266	MHz
f_MCK	Main system bus clock (MCK) frequency	VDDCORE ≥ 1.04V	–	200	MHz

Table 10-6. Recommended Operating Conditions on SDRAM Interface
Symbol	Parameters	Conditions		Min	Max	Unit
f_{SDRAM_CLK}	SDRAM clock frequency	VDDCORE ≥ 1.14V	DDR2-SDRAM	125	266	MHz
			DDR3(L)-SDRAM (DLL ON)⁽¹⁾	266	–	MHz
			DDR3(L)-SDRAM (DLL OFF)⁽²⁾	–	200	MHz
		VDDCORE ≥ 1.04V	DDR2-SDRAM	125	200	MHz
		VDDCORE ≥ 1.04V	DDR3(L)-SDRAM (DLL OFF)⁽²⁾	–	200	MHz

Note:

According to the JEDEC specification, DDR3(L) “DLL On mode” is supported for clock frequencies of 300 MHz and above. Most memory suppliers accept operations down to 266 MHz. Contact the memory supplier for further details.
According to the JEDEC specification, DDR3(L) “DLL Off mode” is supported for clock frequencies up to 125 MHz. Most memory suppliers accept operations up to 200 MHz. Contact the memory supplier for further details.

Table 10-7. Recommended Thermal Operating Conditions
Symbol	Parameter	Conditions	Min	Max	Unit
T_A	Ambient temperature range	SAM9X7x-I devices	-40	85	°C
T_A	Ambient temperature range	SAM9X7x-V devices	-40	105	°C
T_J	Junction temperature range	–	-40	125	°C

Table 10-8. Package Characteristics ─ SAM9X7x-I Devices
Symbol	Parameter	Conditions	Min	Unit
R_JA	Junction-to-ambient thermal resistance	–	38	°C/W
R_JC	Junction-to-case thermal resistance	–	16	°C/W
R_JB	Junction-to-board thermal resistance	–	31	°C/W
Ψ_J-top	Junction-to-case thermal resistance	–	0.57	°C/W

Note: The package characteristics in the above table are provided according to the JEDEC JESD51-2 standard with the 2s2p board and 0 m/s air flow. These values are not directly applicable to the final application. As per JEDEC standards, these parameters represent the device mounted on a specific PCB under controlled conditions. In real-world applications, the PCB design and construction, airflow, and other factors can significantly impact thermal characteristics.

Table 10-9. Package Characteristics ─ SAM9X7x-V Devices ─ BGA240
Symbol	Parameter	Conditions	Min	Unit
R_JA	Junction-to-ambient thermal resistance	–	33	°C/W
R_JC	Junction-to-case thermal resistance	–	12	°C/W
R_JB	Junction-to-board thermal resistance	–	26	°C/W
Ψ_J-top	Junction-to-case thermal resistance	–	0.45	°C/W

Table 10-10. Package Characteristics ─ SAM9X7x-V Devices ─ BGA256
Symbol	Parameter	Conditions	Min	Unit
R_JA	Junction-to-ambient thermal resistance	–	34	°C/W
R_JC	Junction-to-case thermal resistance	–	17	°C/W
R_JB	Junction-to-board thermal resistance	–	25	°C/W
Ψ_J-top	Junction-to-case thermal resistance	–	0.4	°C/W