1.8.2.3 Pin Description

The device features several PIO controllers that multiplex the I/O lines of the peripheral set. The following Pin Description table defines how the I/O lines are multiplexed on the different PIO controllers. The "Reset State" column shows whether the PIO line resets in I/O mode or in Peripheral mode. If I/O is shown, the PIO line resets with the characteristics (input, output, pull-up or pull-down) indicated in this same column, so that the device is configured in a known state as soon as the reset is released. As a result, PIO_CFGR.FUNC resets to ‘0’. If a signal name is shown in the “Reset State” column, the PIO line is assigned to this function and PIO_CFGR.FUNC is not set to ‘0’. That is the case for pins controlling memories, in particular address lines, which require the pin to be driven as soon as the reset is released.

Table 1-3. Pin Description(1)

240-pin
BGA

256-pin
BGA

Power Rail

I/O
Type

(2)
PrimaryAlternatePIO PeripheralReset State(4)
SignalDirSignalDirFuncSignalDir

I/O
Set

(3)

Signal, Dir,
PU, PD, HiZ,
ST, SEC,
FILTER

T9U9VDDIOP0GPIOPA0I/OASDMMC0_DAT0I/O1PIO, I, PU, ST
N8P9VDDIOP0GPIOPA1I/OASDMMC0_CMDI/O1PIO, I, PU, ST
T8R7VDDIOP0GPIOPA2I/OWKUP1ASDMMC0_CKI/O1PIO, I, PU, ST
P6U8VDDIOP0GPIOPA3I/OASDMMC0_DAT1I/O1PIO, I, PU, ST
R8T7VDDIOP0GPIOPA4I/OASDMMC0_DAT2I/O1PIO, I, PU, ST
N3N9VDDIOP0GPIOPA5I/OASDMMC0_DAT3I/O1PIO, I, PU, ST
T7U7VDDIOP0GPIOPA6I/OAFLEXCOM0_IO4O1PIO, I, PU, ST
BSDMMC1_DAT1I/O1
P5L8VDDIOP0GPIOPA7I/OWKUP2AFLEXCOM0_IO3I/O1PIO, I, PU, ST
BSDMMC1_DAT2I/O1
T6U6VDDIOP0GPIOPA8I/OWKUP3AFLEXCOM0_IO2I/O1PIO, I, PU, ST
BSDMMC1_DAT3I/O1
P4P8VDDIOP0GPIOPA9I/OAFLEXCOM4_IO1I/O1,2PIO, I, PU, ST
BSDMMC1_DAT0I/O1
R7T6VDDIOP0GPIOPA10I/OAFLEXCOM4_IO0I/O1,2PIO, I, PU, ST
BSDMMC1_CMDI/O1
M8N7VDDIOP0GPIOPA11I/OAFLEXCOM4_IO2I/O1,2PIO, I, PU, ST
BSDMMC1_CKI/O1
R6R6VDDIOP0GPIOPA12I/OAFLEXCOM4_IO3I/O1,2PIO, I, PU, ST
CFLEXCOM5_IO4O1
N5U5VDDIOP0GPIOPA13I/OAFLEXCOM2_IO0I/O1PIO, I, PU, ST
BFLEXCOM4_IO4O1
T5T5VDDIOP0GPIOPA14I/OAFLEXCOM2_IO1I/O1PIO, I, PU, ST
BFLEXCOM5_IO3I/O1,2
CFLEXCOM4_IO5O1
H3P7VDDIOP0GPIOPA15I/OATIOA0I/O1PIO, I, PU, ST
BFLEXCOM5_IO1I/O1,2
CCLASSD_R0O1
N6R5VDDIOP0GPIOPA16I/OATIOA1I/O1PIO, I, PU, ST
BFLEXCOM5_IO0I/O1,2
CCLASSD_R1O1
R5R4VDDIOP0GPIOPA17I/OATIOA2I/O1PIO, I, PU, ST
BFLEXCOM5_IO2I/O1,2
CCLASSD_R2O1
J4K7VDDIOP0GPIOPA18I/OATCLK0I1PIO, I, PU, ST
BTKI/O1
CCLASSD_L0O1
T4U4VDDIOP0GPIOPA19I/OATCLK1I1PIO, I, PU, ST
BTFI/O1
CCLASSD_L1O1
M6T4VDDIOP0GPIOPA20I/OWKUP4ATCLK2I1PIO, I, PU, ST
BTDO1
CCLASSD_L2O1
J3L5VDDIOP0GPIOPA21I/OATIOB0I/O1PIO, I, PU, ST
BRDI1
CCLASSD_L3O1
T3U3VDDIOP0GPIOPA22I/OATIOB1I/O1PIO, I, PU, ST
BRKI/O1
CCLASSD_R3O1
R4P4VDDIOP0GPIOPA23I/OATIOB2I/O1PIO, I, PU, ST
BRFI/O1
CFLEXCOM2_IO7I1
M3J5VDDANAGPIOPA24I/OAD0AFLEXCOM6_IO0I/O1PIO, I, PU, ST
BFLEXCOM5_IO6O1
M1N4VDDANAGPIOPA25I/OAD1AFLEXCOM6_IO1I/O1PIO, I, PU, ST
BFLEXCOM5_IO5O1
L3K5VDDANAGPIOPA26I/OAD2ADRXDI1PIO, I, PU, ST
BCANRX0I1
L2P3VDDANAGPIOPA27I/OAD3ADTXDO1PIO, I, PU, ST
BCANTX0O1
M4M4VDDANAGPIOPA28I/OAD4AFLEXCOM1_IO0I/O1PIO, I, PU, ST
BCANTX1O1
L4N3VDDANAGPIOPA29I/OAD5AFLEXCOM1_IO1I/O1PIO, I, PU, ST
BCANRX1I1
L1N5VDDANAGPIOPA30I/OAD6AFLEXCOM0_IO0I/O1PIO, I, PU, ST
BFLEXCOM5_IO4O2
CFLEXCOM4_IO4O2
M2P2VDDANAGPIOPA31I/OAD7AFLEXCOM0_IO1I/O1PIO, I, PU, ST
BFLEXCOM4_IO5O2
CGTSUCOMPO1
R13R12VDDIOP2GPIOPB0I/OWKUP5AGRX2I1PIO, I, PU, ST
BFLEXCOM2_IO4O1
CGRXERI1
N11N12VDDIOP2GPIOPB1I/OAGRX3I1PIO, I, PU, ST
BFLEXCOM2_IO3I/O1
R12T12VDDIOP2GPIOPB2I/OAG125CKI1PIO, I, PU, ST
BFLEXCOM2_IO2I/O1
T10R11VDDIOP2GPIOPB3I/OWKUP6AGCRSDV/GRXCTLI1PIO, I, PU, ST
BFLEXCOM4_IO6O1
T13U12VDDIOP2GPIOPB4I/OAGTX2O1PIO, I, PU, ST
BFLEXCOM8_IO0I/O1
N9P12VDDIOP2GPIOPB5I/OAGTX3O1PIO, I, PU, ST
BFLEXCOM8_IO1I/O1
R11T10VDDIOP2GPIOPB6I/OAGTXCK/GREFCKI/O1PIO, I, PU, ST
BFLEXCOM0_IO7I1
M9P11VDDIOP2GPIOPB7I/OAGTXEN/GTXCTLO1PIO, I, PU, ST
CFLEXCOM6_IO2I/O1
T12U11VDDIOP2GPIOPB8I/OAGRXCKI1PIO, I, PU, ST
CFLEXCOM6_IO3I/O1
P8R10VDDIOP2GPIOPB9I/OAGMDIOI/O1PIO, I, PU, ST
BPCK1O1
CFLEXCOM6_IO4O1
R10T9VDDIOP2GPIOPB10I/OAGMDCO1PIO, I, PU, ST
BPCK0O1
CFLEXCOM8_IO2I/O1
L9N10VDDIOP2GPIOPB11I/OAGRX0I1PIO, I, PU, ST
BPWM0O2
CFLEXCOM8_IO3I/O1
T11U10VDDIOP2GPIOPB12I/OAGRX1I1PIO, I, PU, ST
BPWM1O2
CFLEXCOM8_IO4O1
P9P10VDDIOP2GPIOPB13I/OAGTX0O1PIO, I, PU, ST
BPWM2O2
R9T8VDDIOP2GPIOPB14I/OAGTX1O1PIO, I, PU, ST
BPWM3O2
C9C9VDDQSPIGPIOPB15I/OAQIO5I/O1PIO, I, PU, ST
B
CFLEXCOM11_IO0I/O1
DI2SMCC_WSI/O1
D9E11VDDQSPIGPIOPB16I/OAQIO6I/O1PIO, I, PU, ST
B
CFLEXCOM11_IO1I/O1
DI2SMCC_DINI1
A11C10VDDQSPIGPIOPB17I/OAQIO7I/O1PIO, I, PU, ST
CFLEXCOM12_IO0I/O1
DI2SMCC_DOUTO1
E9C11VDDQSPIGPIOPB18I/OWKUP7AQDQSI1PIO, I, PU, ST
BADTRGI1
CFLEXCOM12_IO1I/O1
DIRQI1
B11A12VDDQSPIGPIOPB19I/OAQSCKO1PIO, I, PU, ST
CFLEXCOM12_IO2I/O1
D11D11VDDQSPIGPIOPB20I/OAQCSO1PIO, I, PU, ST
CFLEXCOM12_IO3I/O1
C11B12VDDQSPIGPIOPB21I/OAQIO0I/O1PIO, I, PU, ST
CFLEXCOM12_IO4O1
E11E12VDDQSPIGPIOPB22I/OAQIO1I/O1PIO, I, PU, ST
CFLEXCOM9_IO2I/O1
B12B13VDDQSPIGPIOPB23I/OAQIO2I/O1PIO, I, PU, ST
CFLEXCOM9_IO3I/O1
C12D12VDDQSPIGPIOPB24I/OAQIO3I/O1PIO, I, PU, ST
CFLEXCOM9_IO4O1
A12A13VDDQSPIGPIOPB25I/OWKUP8AQINTI1PIO, I, PU, ST
DI2SMCC_MCKO1
D12C13VDDQSPIGPIOPB26I/OAQIO4I/O1PIO, I, PU, ST
DI2SMCC_CKI/O1
D3B3VDDIOP1GPIOPC0I/OALCDC_DAT0O1PIO, I, PU, ST
BISC_D0I1
CFLEXCOM7_IO0I/O1
F3C3VDDIOP1GPIOPC1I/OALCDC_DAT1O1PIO, I, PU, ST
BISC_D1I1
CFLEXCOM7_IO1I/O1
A6A7VDDLVDSGPIOPC2I/OLVDS_A0MALCDC_DAT2O1PIO, I, PU, ST
BISC_D2I1
CTIOA3I/O1
B6B7VDDLVDSGPIOPC3I/OLVDS_A0PALCDC_DAT3O1PIO, I, PU, ST
BISC_D3I1
CTIOB3I/O1
A7A8VDDLVDSGPIOPC4I/OLVDS_A1MALCDC_DAT4O1PIO, I, PU, ST
BISC_D4I1
CTCLK3I1
B7B8VDDLVDSGPIOPC5I/OLVDS_A1PALCDC_DAT5O1PIO, I, PU, ST
BISC_D5I1
CTIOA4I/O1
A8A9VDDLVDSGPIOPC6I/OLVDS_A2MALCDC_DAT6O1PIO, I, PU, ST
BISC_D6I1
CTIOB4I/O1
B8B9VDDLVDSGPIOPC7I/OLVDS_A2PALCDC_DAT7O1PIO, I, PU, ST
BISC_D7I1
CTCLK4I1
A2A2VDDIOP1GPIOPC8I/OALCDC_DAT8O1PIO, I, PU, ST
BISC_D8I1
CFLEXCOM9_IO0I/O1
D6D3VDDIOP1GPIOPC9I/OALCDC_DAT9O1PIO, I, PU, ST
BISC_D9I1
CFLEXCOM9_IO1I/O1
A9A10VDDLVDSGPIOPC10I/OLVDS_CLK1MALCDC_DAT10O1PIO, I, PU, ST
BISC_D10I1
CPWM0O3
B9B10VDDLVDSGPIOPC11I/OLVDS_CLK1PALCDC_DAT11O1PIO, I, PU, ST
BISC_D11I1
CPWM1O3
A10A11VDDLVDSGPIOPC12I/OLVDS_A3MALCDC_DAT12O1PIO, I, PU, ST
BISC_PCKI1
CTIOA5I/O1
B10B11VDDLVDSGPIOPC13I/OLVDS_A3PALCDC_DAT13O1PIO, I, PU, ST
BISC_VSYNCI1
CTIOB5I/O1
C4A3VDDIOP1GPIOPC14I/OALCDC_DAT14O1PIO, I, PU, ST
BISC_HSYNCI1
CTCLK5I1
D4D5VDDIOP1GPIOPC15I/OALCDC_DAT15O1PIO, I, PU, ST
BISC_MCKO1
CPCK0O2
C5C4VDDIOP1GPIOPC16I/OALCDC_DAT16O1PIO, I, PU, ST
BISC_FIELDI1
CFLEXCOM10_IO0I/O1
F4B4VDDIOP1GPIOPC17I/OALCDC_DAT17O1PIO, I, PU, ST
BFLEXCOM1_IO7I1
CFLEXCOM10_IO1I/O1
B3A4VDDIOP1GPIOPC18I/OALCDC_DAT18O1PIO, I, PU, ST
BFLEXCOM10_IO2I/O1
CPWM0O1
E4E6VDDIOP1GPIOPC19I/OALCDC_DAT19O1PIO, I, PU, ST
BFLEXCOM10_IO3I/O1
CPWM1O1
A3A5VDDIOP1GPIOPC20I/OALCDC_DAT20O1PIO, I, PU, ST
BFLEXCOM10_IO4O1
CPWM2O1
E3D7VDDIOP1GPIOPC21I/OALCDC_DAT21O1PIO, I, PU, ST
CPWM3O1
B4C5VDDIOP1GPIOPC22I/OALCDC_DAT22O1PIO, I, PU, ST
BFLEXCOM3_IO0I/O1
C6B5VDDIOP1GPIOPC23I/OWKUP9ALCDC_DAT23O1PIO, I, PU, ST
BFLEXCOM3_IO1I/O1
A4C6VDDIOP1GPIOPC24I/OWKUP10ALCDC_DISPO1PIO, I, PU, ST
BFLEXCOM3_IO4O1
E6E7VDDIOP1GPIOPC25I/OWKUP12ANTRSTI1NRST_OUT, O, PD
BFLEXCOM3_IO3I/O1
CNRST_OUTO1
B5A6VDDIOP1GPIOPC26I/OWKUP13ALCDC_PWMO1PIO, I, PU, ST
BFLEXCOM3_IO2I/O1
E8G7VDDIOP1GPIOPC27I/OALCDC_VSYNCO1PIO, I, PU, ST
CFLEXCOM1_IO4O1
A5B6VDDIOP1GPIOPC28I/OALCDC_HSYNCO1PIO, I, PU, ST
CFLEXCOM1_IO3I/O1
D8G8VDDIOP1GPIOPC29I/OALCDC_DENO1PIO, I, PU, ST
CFLEXCOM1_IO2I/O1
C8C7VDDIOP1GPIOPC30I/OALCDC_PCKO1PIO, I, PU, ST
CFLEXCOM3_IO7I1
F9D9VDDIOP1GPIOPC31I/OWKUP11AFIQI1PIO, I, PU, ST
CPCK1O2
R16P15VDDNFGPIOPD0I/OANANDOEO1PIO, I, PU
CFLEXCOM7_IO2I/O1
N16R17VDDNFGPIOPD1I/OANANDWEO1PIO, I, PU
CFLEXCOM7_IO3I/O1
P15P17VDDNFGPIOPD2I/OAA21/NANDALEO1A21,O, PD
CFLEXCOM7_IO4O1
P16T17VDDNFGPIOPD3I/OAA22/NANDCLEO1A22,O, PD
CFLEXCOM11_IO2I/O1
N15P14VDDNFGPIOPD4I/OANCS2/NANDCSO1PIO, I, PU
CFLEXCOM11_IO3I/O1
N14U16VDDNFGPIOPD5I/OAPIO, I, PU
BNCS0O1
CFLEXCOM11_IO4O1
R15R15VDDNFGPIOPD6I/OANANDDAT0I/O1PIO, I, PU
BA1O1
P12T15VDDNFGPIOPD7I/OANANDDAT1I/O1PIO, I, PU
BA12O1
P13U15VDDNFGPIOPD8I/OANANDDAT2I/O1PIO, I, PU
BA19O1
N12R13VDDNFGPIOPD9I/OANANDDAT3I/O1PIO, I, PU
BA20O1
R14T13VDDNFGPIOPD10I/OANANDDAT4I/O1PIO, I, PU
BNRDO1
M11T14VDDNFGPIOPD11I/OANANDDAT5I/O1PIO, I, PU
BNWR0/NWEO1
T14U14VDDNFGPIOPD12I/OANANDDAT6I/O1PIO, I, PU
BA0/NBS0O1
P11P13VDDNFGPIOPD13I/OANANDDAT7I/O1PIO, I, PU
BNWR1/NBS1O1
T15U13VDDNFGPIOPD14I/OANWAIT/NANDRDYI1PIO, I, PU
E12G14VDDIOMPowerVDDIOMI
G12J11VDDIOMPowerVDDIOMI
K12K11VDDIOMPowerVDDIOMI
M12K14VDDIOMPowerVDDIOMI
G6D4VDDMIPIPowerVDDMIPII
D10E9VDDLVDSPowerVDDLVDSI
N13R16VDDNFPowerVDDNFI
N7R8VDDIOP0PowerVDDIOP0I
D7D8VDDIOP1PowerVDDIOP1I
N10T11VDDIOP2PowerVDDIOP2I
C13C12VDDQSPIPowerVDDQSPII
N4U2VDDBUPowerVDDBUI
M5P5VDDBUPowerVDDBUI
L7K4VDDANAPowerVDDANAI
K5M3GNDANAGroundGNDANAI
F8C8VDDOUT25PowerVDDOUT25I
G4G5VDDIN33PowerVDDIN33I
K4K3VDDIN33PowerVDDIN33I
D5D6VDDCOREPowerVDDCOREI
E5E5VDDCOREPowerVDDCOREI
F7F5VDDCOREPowerVDDCOREI
F10F13VDDCOREPowerVDDCOREI
L10F14VDDCOREPowerVDDCOREI
A1A1GNDGroundGNDI
T1J3GNDGroundGNDI
C3D10GNDGroundGNDI
G3H3GNDGroundGNDI
K3L1GNDGroundGNDI
P3H4GNDGroundGNDI
G5F3GNDGroundGNDI
C7D13GNDGroundGNDI
E7E4GNDGroundGNDI
M7G11GNDGroundGNDI
P7H5GNDGroundGNDI
H8GNDGroundGNDI
J8GNDGroundGNDI
L8G10GNDGroundGNDI
H9GNDGroundGNDI
C10E10GNDGroundGNDI
E10E8GNDGroundGNDI
M10G13GNDGroundGNDI
P10H11GNDGroundGNDI
G11E13GNDGroundGNDI
K11G2GNDGroundGNDI
G13G1GNDGroundGNDI
K13G9GNDGroundGNDI
C14E3GNDGroundGNDI
P14H13GNDGroundGNDI
A16GNDGroundGNDI
T16K13GNDGroundGNDI
G14E15VDDIOMDDRIOD0O, PD
D16F16VDDIOMDDRIOD1O, PD
E15E16VDDIOMDDRIOD2O, PD
E14D15VDDIOMDDRIOD3O, PD
E16C17VDDIOMDDRIOD4O, PD
E13E14VDDIOMDDRIOD5O, PD
D15D16VDDIOMDDRIOD6O, PD
F12D17VDDIOMDDRIOD7O, PD
C16C15VDDIOMDDRIOD8O, PD
D14C16VDDIOMDDRIOD9O, PD
D13D14VDDIOMDDRIOD10O, PD
B16B16VDDIOMDDRIOD11O, PD
A14B15VDDIOMDDRIOD12O, PD
B13C14VDDIOMDDRIOD13O, PD
B14B14VDDIOMDDRIOD14O, PD
A13A14VDDIOMDDRIOD15O, PD
L13K16VDDIOMDDRIOA2O, PD
L15L15VDDIOMDDRIOA3O, PD
L14M16VDDIOMDDRIOA4O, PD
K14K15VDDIOMDDRIOA5O, PD
L16L16VDDIOMDDRIOA6O, PD
K15J15VDDIOMDDRIOA7O, PD
K16H16VDDIOMDDRIOA8O, PD
M14P16VDDIOMDDRIOA9O, PD
M15N15VDDIOMDDRIOA10O, PD
M13M15VDDIOMDDRIOA11O, PD
M16N17VDDIOMDDRIOA13O, PD
J15N16VDDIOMDDRIOA14O, PD
H15H15VDDIOMDDRIOA15O, PD
L12G15VDDIOMDDRIOA16BA0O, PD
J16G16VDDIOMDDRIOA17BA1O, PD
G15F15VDDIOMDDRIOA18BA2O, PD
H16J17VDDIOMDDRIONCS1DDRCSO, PU
J14L17VDDIOMDDRIOSDCKO, PD
J13M17VDDIOMDDRIOSDCKNO, PU
G16H17VDDIOMDDRIOSDCKEO, PU
H13J14VDDIOMDDRIORASO, PU
H14J16VDDIOMDDRIOCASO, PU
H12J13VDDIOMDDRIOSDWEO, PU
J12L13VDDIOMDDRIOSDA10O, PU
F15E17VDDIOMDDRIODQM0O, PU
C15B17VDDIOMDDRIODQM1O, PU
F13G17VDDIOMDDRIODQS0O, PD
F14F17VDDIOMDDRIONDQS0O, PU
B15A16VDDIOMDDRIODQS1O, PD
A15A15VDDIOMDDRIONDQS1O, PU
H11M14VDDIOManalogDDR_CALII
F16K17VDDIOManalogDDR_VREFII
J11H14VDDIOMDDRIORESETNO
N2N1VDDANAGPIOADVREFPI
N1N2VDDANAGPIOADVREFNI
K6M2VDDIN33USBHSHHSRTUNEI
H2H2VDDIN33USBHSHHSDPADHSDPO, PD
H1H1VDDIN33USBHSHHSDMADHSDMO, PD
J2J2VDDIN33USBHSHHSDPBO, PD
J1J1VDDIN33USBHSHHSDMBO, PD
K2K2VDDIN33USBHSHHSDPCO, PD
K1K1VDDIN33USBHSHHSDMCO, PD
L5T3VDDBUGPIOWKUP0I, ST
J6H7VDDBUGPIOSHDNO, PD
P1P1VDDBUGPIOJTAGSELI, PD
J9R1VDDBUGPIOTSTI, PD, ST
H5L7VDDIOP0GPIOTCKI, ST
H4J7VDDIOP0GPIOTDII, ST
T2N6VDDIOP0GPIOTDOO
P2R2VDDIOP0GPIOTMSI, ST
R3R3VDDIOP0GPIORTCKO
F5M5VDDIOP0GPIONRSTI, PU, ST
R2T1VDDBUCLOCKXIN32I
R1T2VDDBUCLOCKXOUT32O
G1G3VDDIN33CLOCKXINI
G2G4VDDIN33CLOCKXOUTO
B1B1VDDMIPIAnalogMIPI_DN0I/OHiZ(5)
B2B2VDDMIPIAnalogMIPI_DP0I/OHiZ(5)
C1C1VDDMIPIAnalogMIPI_DN1I/OHiZ(5)
C2C2VDDMIPIAnalogMIPI_DP1I/OHiZ(5)
E1E1VDDMIPIAnalogMIPI_DN2I/OHiZ(5)
E2E2VDDMIPIAnalogMIPI_DP2I/OHiZ(5)
F1F1VDDMIPIAnalogMIPI_DN3I/OHiZ(5)
F2F2VDDMIPIAnalogMIPI_DP3I/OHiZ(5)
D1D1VDDMIPIAnalogMIPI_CLKNOHiZ(5)
D2D2VDDMIPIAnalogMIPI_CLKPOHiZ(5)
H6F4VDDMIPIAnalogMIPI_REXTII(5)
J5L4VDDANAGPIOAUDIOCLKO
L10VDDCOREPower
L11VDDCOREPower
J4VDDOUT25Power
L2VDDANAPower
M1VDDANAPower
N14VDDIOMPower
L3GNDGround
L9GNDGround
L14GNDGround
M13GNDGround
N8GNDGround
N11GNDGround
N13GNDGround
P6GNDGround
R9GNDGround
R14GNDGround
T16GNDGround
U1GNDGround
U17GNDGround
Note:
  1. When using an I/O line with the Analog-to-Digital Converter (ADC), the PIO line configuration (pull-up, pull-down) programmed before assigning this line to the ADC peripheral is not modified by this peripheral.
  2. Refer to the Electrical Characteristics section for further details.
  3. I/Os for each peripheral are grouped into I/O sets, listed in the column "I/O Set". For all peripherals, use I/Os that belong to the same I/O set. Timings can be unpredictable when I/Os from different I/O sets are mixed.

  4. Signal = ‘PIO’ if GPIO; Dir = Direction; PU = Pull-up; PD = Pull-down; HiZ = High impedance; ST = Schmitt Trigger
  5. On SAM9X70 and SAM9X72: to be tied to GND.