High-Speed Data Reception Mode

High-speed data reception occurs in bursts. Only during these bursts is the lane in High-Speed mode. A high-speed burst must start from and return to a Stop state (Control mode).

Each data lane can receive a high-speed transmission independently of the state of the remaining data lanes.

A burst contains the low-power initialization sequence, the high-speed data payload, and the end-of-transmission sequence.

Figure 5-58. HS Data Reception Sequence

The D-PHY receiver enters High-Speed mode following the sequence of low-power states in the lines LP-11, LP-01, and LP-00. This sequence is seen as a High-Speed mode request, and toggles the enabling of the high-speed receivers. Synchronization is then achieved through the identification of the leader sequence in the received differential high-speed data. Once the synchronization is achieved, the D-PHY outputs the received bytes through the protocol layer, until a Stop state (LP-11) is detected in the lane.