8.3.9.6.10 FIFO Overflow/Underflow Error

If the Transmit FIFO is full and a write access is performed on FLEX_TWI_THR, it generates a Transmit FIFO overflow error and sets FLEX_TWI_FSR.TXFPTEF.

If the number of data written in FLEX_TWI_THR (according to the register access size) is greater than the free space in the Transmit FIFO, a Transmit FIFO overflow error is generated and FLEX_TWI_FSR.TXFPTEF is set.

If the number of bytes read in FLEX_TWI_RHR (according to the register access size) is greater than the number of unread bytes in the Receive FIFO, a Receive FIFO underflow error is generated and FLEX_TWI_FSR.RXFPTEF is set.

No error occurs if the FIFO state/level is checked before writing/reading in FLEX_TWI_THR/FLEX_TWI_RHR. The FIFO state/level can be checked either with TXRDY, RXRDY, TXFL or RXFL. When such error occurs, other FIFO flags may not behave as expected; their states should be ignored. A software reset must be performed using FLEX_TWI_CR.SWRST. Note that issuing a software reset during transmission may leave a client in an unknown state holding the TWD line. In this case, a Bus Clear command may instruct the client to release the TWD line (the first frame sent afterward may not be received properly by the client). See Bus Clear Command to initiate the Bus Clear command.