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Arm® Arm926EJ-S™ Processor-Based MPU, 800 MHz, MIPI DSI® or CSI-2, LVDS, RGB, 2D Graphics, Gigabit Ethernet with TSN, CAN-FD, Octal/Quad SPI, Crypto, PUF
Arm® Arm926EJ-S™ Processor-Based MPU, 800 MHz, MIPI DSI® or CSI-2, LVDS, RGB, 2D Graphics, Gigabit Ethernet with TSN, CAN-FD, Octal/Quad SPI, Crypto, PUF
Product Pages
SAM9X70 SAM9X72 SAM9X75
  1. Home
  2. 8 Connectivity Subsystem
  3. 8.3 Flexible Serial Communication Controller (FLEXCOM)
  4. 8.3.9 TWI Functional Description
  5. 8.3.9.6 TWI FIFOs
  6. 8.3.9.6.4 Sending/Receiving with FIFO Enabled in Client Mode

  • Introduction
  • Reference Document
  • 1 Overview
  • 2 CPU and Interconnect
  • 3 Memories
  • 4 System Controller
  • 5 Image Subsystem
  • 6 Audio Subsystem
  • 7 Security and Cryptography Subsystem
  • 8 Connectivity Subsystem
    • 8.1 Overview
    • 8.2 Ethernet MAC (GMAC)
    • 8.3 Flexible Serial Communication Controller (FLEXCOM)
      • 8.3.1 Description
      • 8.3.2 Embedded Characteristics
      • 8.3.3 Block Diagram
      • 8.3.4 I/O Lines Description
      • 8.3.5 Product Dependencies
      • 8.3.6 Register Accesses
      • 8.3.7 USART Functional Description
      • 8.3.8 SPI Functional Description
      • 8.3.9 TWI Functional Description
        • 8.3.9.1 Transfer Format
        • 8.3.9.2 Modes of Operation
        • 8.3.9.3 Host Mode
        • 8.3.9.4 Multi-Host Mode
        • 8.3.9.5 Client Mode
        • 8.3.9.6 TWI FIFOs
          • 8.3.9.6.1 Overview
          • 8.3.9.6.2 Sending Data with FIFO Enabled
          • 8.3.9.6.3 Receiving Data with FIFO Enabled
          • 8.3.9.6.4 Sending/Receiving with FIFO Enabled in Client Mode
          • 8.3.9.6.5 Clearing/Flushing FIFOs
          • 8.3.9.6.6 TXRDY and RXRDY Behavior
          • 8.3.9.6.7 TWI Single Data Access
          • 8.3.9.6.8 TWI Multiple Data Access
          • 8.3.9.6.9 Transmit FIFO Lock
          • 8.3.9.6.10 FIFO Overflow/Underflow Error
          • 8.3.9.6.11 FIFO Thresholds
          • 8.3.9.6.12 FIFO Flags
        • 8.3.9.7 TWI Comparison Function on Received Character
        • 8.3.9.8 Sniffer Mode
        • 8.3.9.9 TWI Register Write Protection
      • 8.3.10 Register Summary
    • 8.4 Quad Serial Peripheral Interface (QSPI)
    • 8.5 Secure Digital MultiMedia Card Controller (SDMMC)
    • 8.6 Controller Area Network (MCAN)
    • 8.7 Timer Counter (TC)
    • 8.8 Pulse Width Modulation Controller (PWM)
  • 9 USB Subsystem
  • 10 Electrical and Mechanical Characteristics
  • 11 Revision History
  • Microchip Information

8.3.9.6.4 Sending/Receiving with FIFO Enabled in Client Mode

See Sending Data with FIFO Enabled and Receiving Data with FIFO Enabled for details.

Figure 8-148. Sending/Receiving Data with FIFO Enabled in Client Mode

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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