8.7.3 Block Diagram
Name | Definition |
---|---|
TIMER_CLOCK1 | GCLK [17], GCLK[45] |
TIMER_CLOCK2 | MCK/8 |
TIMER_CLOCK3 | MCK/32 |
TIMER_CLOCK4 | MCK/128 |
TIMER_CLOCK5 (1) | MD_SLCK |
Note:
- The GCLK [TC_ID] frequency must be at least three times lower than peripheral clock frequency.
Note:
- The above figure provides pin names of a first instance of a Timer Counter module (i.e., instance TC0). For any subsequent instances, the signal numbering increments. For example, “TCLK3- TCLK5”, "TIOA3-TIOA5” and "TIOB3-TIOB5” are the external I/O pins of a second Timer Counter module (i.e., instance TC1).
- QDEC connections are detailed in Figure 8-229.
Signal Name | Description |
---|---|
XC0, XC1, XC2 | Channel clock source that can be connected to TIOAx, TIOBx, TCLKx |
TIMER_CLOCK1-5 | Channel clock source from system clocks |
TIOAx |
Capture mode: Timer Counter input Waveform mode: Timer Counter output |
TIOBx |
Capture mode: Timer Counter input Waveform mode: Timer Counter input/output |
INT | Interrupt signal output (internal signal) |
SYNC | Synchronization input signal (from Configuration register) |