SCL Rising Time Control

In order to meet the TWI High-Speed mode SCL rise time requirements, the SCL Rise Boost feature is enabled automatically when TWI High-Speed mode is enabled.

SCLRBL bit in FLEX_TWI_MMR enables to set the number of system clock periods (MCK) during which the SCL signal will be directly driven to level ‘1’ when the SCL rising edge is sent. This short time during which the SCL pin is directly driven to level ‘1’ allows to increase the SCL slope as much as needed to meet the High-Speed mode rise time requirements.

The SCL Rise Boost feature can be enabled with FLEX_TWI_CR.SCLRBE and disabled with FLEX_TWI_CR.SCLRBD.