2.4.5.5.1 Single Block Transfer With Single Microblock
- Read the XDMAC Global Channel Status Register (XDMAC_GS) to select a free channel.
- Clear the pending Interrupt Status bit(s) by reading the selected XDMAC Channel x Interrupt Status Register (XDMAC_CISx).
- Write the XDMAC Channel x Source Address Register (XDMAC_CSAx) for channel x.
- Write the XDMAC Channel x Destination Address Register (XDMAC_CDAx) for channel x.
- Program field UBLEN in the XDMAC Channel x Microblock Control Register (XDMAC_CUBCx) with the number of data.
- Program the XDMAC Channel x Configuration Register
(XDMAC_CCx):
- Clear XDMAC_CCx.TYPE for a memory-to-memory transfer, otherwise set this bit.
- Configure XDMAC_CCx.MBSIZE to the memory burst size used.
- Configure XDMAC_CCx.SAM and DAM to Memory Addressing mode.
- Configure XDMAC_CCx.DSYNC to select the peripheral transfer direction.
- Configure XDMAC_CCx.CSIZE to configure the channel chunk size (only relevant for peripheral synchronized transfer).
- Configure XDMAC_CCx.DWIDTH to configure the transfer data width.
- Configure XDMAC_CCx.SIF, XDMAC_CCx.DIF to configure the host interface used to read data and write data, respectively.
- Configure XDMAC_CCx.PERID to select the active hardware request line (only relevant for a peripheral synchronized transfer).
- Set XDMAC_CCx.SWREQ to use a software request (only relevant for a peripheral synchronized transfer).
- Clear the following five registers:
- XDMAC Channel x Next Descriptor Control Register (XDMAC_CNDCx)
- XDMAC Channel x Block Control Register (XDMAC_CBCx)
- XDMAC Channel x Data Stride Memory Set Pattern Register (XDMAC_CDS_MSPx)
- XDMAC Channel x Source Microblock Stride Register (XDMAC_CSUSx)
- XDMAC Channel x Destination Microblock Stride Register
(XDMAC_CDUSx)
This indicates that the linked list is disabled, there is only one block and striding is disabled.
- Enable the Microblock interrupt by writing a ‘1’ to bit BIE in the XDMAC Channel x Interrupt Enable Register (XDMAC_CIEx). Enable the Channel x Interrupt Enable bit by writing a ‘1’ to bit IEx in the XDMAC Global Interrupt Enable Register (XDMAC_GIE).
- Enable channel x by writing a ‘1’ to bit ENx in the XDMAC Global Channel Enable Register (XDMAC_GE). XDMAC_GS.STx (XDMAC Channel x Status bit) is set by hardware.
- Once completed, the DMA channel sets XDMAC_CISx.BIS (End of Block Interrupt Status bit) and generates an interrupt. XDMAC_GS.STx is cleared by hardware. The software can either wait for an interrupt or poll the channel status bit.