2.3.9.4 MATRIX Priority Register B For Clients x

Table 2-9. MATRIX_PRBSx Register Reset Values
RegistersReset Values
PRBS0, PRBS4, PRBS70x00000000
PRBS1, PRBS5, PRBS6, PRBS10, PRBS110x00110000
PRBS20x00010000
PRBS3, PRBS8, PRBS90x00100000

This register can only be written if the WPEN bit is cleared in the Write Protection Mode Register.

Name: MATRIX_PRBSx
Offset: 0x84 + x*0x08 [x=0..11]
Reset: 
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
  LQOSEN13M13PR[1:0] LQOSEN12M12PR[1:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset  
Bit 15141312111098 
  LQOSEN11M11PR[1:0] LQOSEN10M10PR[1:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset  
Bit 76543210 
  LQOSEN9M9PR[1:0] LQOSEN8M8PR[1:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset  

Bits 2, 6, 10, 14, 18, 22 – LQOSENx Latency Quality of Service Enable for Host x

ValueDescription
0

Disables propagation of Latency Quality of Service from the Host x to the Client and apply MxPR priority for all access from Host x to the Client.

1

Enables the propagation of Latency Quality of Service from the Host x to the Client if supported by the Host x.

Bits 0:1, 4:5, 8:9, 12:13, 16:17, 20:21 – MxPR Host x Priority

Fixed priority of Host x for accessing the selected client. The higher the number, the higher the priority.

All the hosts programmed with the same MxPR value for the client make up a priority pool.

Round-robin arbitration is used in the lowest (MxPR = 0) and highest (MxPR = 3) priority pools.

Fixed priority is used in intermediate priority pools (MxPR = 1) and (MxPR = 2).

See Arbitration Priority Scheme for details.

If LQOSENx bit is cleared, then this priority value is used as it for arbitration and downward propagation to the client. If LQOSENx bit is set, then this priority acts as the upper limit for the Latency Quality of Service from Host x.

For hosts other than the CPU, the usual value of this field should be 0x0 if LQOSENx bit is cleared, and 0x1 if LQOSENx bit is set. For the CPU host, the usual value of this field should be 0x2.