2.3.1.1 MATRIX Hosts

The MATRIX manages the 14 hosts listed in the table below. Each host can perform an access, concurrently with others, to an available client. The MATRIX operates at the main system bus clock (MCK) frequency. Each host has its own decoder, which is defined specifically for each host. In order to simplify the addressing, all the hosts have the same decodings.

Table 2-2. List of MATRIX Hosts
Host No.Description
0ISC DMA with QoS support
1LCDC DMA with QoS support
2GMAC DMA
3, 4XDMA controller with QoS support
5GFX2D DMA
6SDMMC0 DMA
7SDMMC1 DMA
8USB high-speed device port (UDPHS) DMA
9USB high-speed host port (UHPHS) EHCI DMA
10USB high-speed host port (UHPHS) OHCI DMA
11Reserved
12Arm926 instruction
13Arm926 data