NAND Flash Boot: NAND Flash Detection

After the NAND Flash interface configuration, a reset command is sent to the memory.

The reset time of the NAND memory, after this reset command, must not be higher than 100 µs.

Hardware ECC detection and correction are provided by the PMECC peripheral. Refer to the section Functional Description in Programmable Multibit Error Correction Code Controller (PMECC) for more details.

The ROM code retrieves NAND Flash parameters and ECC requirements using a specific header store at the beginning of the bootstrap.

Once the ROM code has got the ECC parameters, it reads the first page again, with or without ECC, depending on the usePmecc parameter. Then it looks for a valid code programmed just after the header offset 0xD0. If the code is valid, the program is copied at the beginning of the internal SRAM.