9.4.7.15 ADC Extended Mode Register
This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register.
| Name: | ADC_EMR |
| Offset: | 0x40 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| ADCMODE[1:0] | SIGNMODE[1:0] | TAG | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TRACKX4 | SRCCLK | ASTE | OSR[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CMPFILTER[1:0] | CMPALL | ||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CMPSEL[3:0] | CMPTYPE | CMPMODE[1:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bits 29:28 – ADCMODE[1:0] ADC Running Mode
See Automatic Error Correction for details on ADC Running mode.
| Value | Name | Description |
|---|---|---|
| 0 | NORMAL | Normal mode of operation. |
| 1 | OFFSET_ERROR | Offset Error mode to measure the offset error. See Table 9-10. |
| 2 | GAIN_ERROR_HIGH | Gain Error mode to measure the gain error. See Table 9-10. |
| 3 | GAIN_ERROR_LOW | Gain Error mode to measure the gain error. See Table 9-10. |
Bits 26:25 – SIGNMODE[1:0] Sign Mode
If conversion results are signed and resolution is below 16 bits, the sign is extended up to the bit 15 (for example, 0xF43 for 12-bit resolution will be read as 0xFF43 and 0x467 will be read as 0x0467). See Conversion Results Format.
| Value | Name | Description |
|---|---|---|
| 0 | SE_UNSG_DF_SIGN | Single-Ended channels: Unsigned conversions.Pseudo-differential channels and Differential channels: Signed conversions. |
| 1 | SE_SIGN_DF_UNSG | Single-Ended channels: Signed conversions.Pseudo-differential channels and Differential channels: Unsigned conversions. |
| 2 | ALL_UNSIGNED | All channels: Unsigned conversions. |
| 3 | ALL_SIGNED | All channels: Signed conversions. |
Bit 24 – TAG Tag of ADC_LCDR
| Value | Description |
|---|---|
| 0 | Sets ADC_LCDR.CHNB field to zero. |
| 1 | Appends the channel number to the conversion result in ADC_LCDR. |
Bit 22 – TRACKX4 Tracking Time x4
| Value | Description |
|---|---|
| 0 | The ADC_MR.TRACKTIM field effect is multiplied by 1. |
| 1 | The ADC_MR.TRACKTIM field effect is multiplied by 4. |
Bit 21 – SRCCLK External Clock Selection
| Value | Name | Description |
|---|---|---|
| 0 | PERIPH_CLK | The peripheral clock is the source for the ADC prescaler. |
| 1 | GCLK | GCLK is the source clock for the ADC prescaler, thus the ADC clock can be independent of the core/peripheral clock. |
Bit 20 – ASTE Averaging on Single Trigger Event
| Value | Name | Description |
|---|---|---|
| 0 | MULTI_TRIG_AVERAGE | The average requests several trigger events. |
| 1 | SINGLE_TRIG_AVERAGE | The average requests only one trigger event. |
Bits 18:16 – OSR[2:0] Over Sampling Rate
| Value | Name | Description |
|---|---|---|
| 0 | NO_AVERAGE | No averaging. ADC sample rate is maximum. |
| 1 | OSR4 | 1-bit enhanced resolution by averaging. ADC sample rate divided by 4. |
| 2 | OSR16 | 2-bit enhanced resolution by averaging. ADC sample rate divided by 16. |
| 3 | OSR64 | 3-bit enhanced resolution by averaging. ADC sample rate divided by 64. |
| 4 | OSR256 | 4-bit enhanced resolution by averaging. ADC sample rate divided by 256. |
Bits 13:12 – CMPFILTER[1:0] Compare Event Filtering
Number of consecutive compare events necessary to raise the flag = CMPFILTER+1
When programmed to 0, the flag rises as soon as an event occurs.
See Comparison Windows when using the filtering option (CMPFILTER > 0).
Bit 9 – CMPALL Compare All Channels
| Value | Description |
|---|---|
| 0 | Only channel indicated in CMPSEL field is compared. |
| 1 | All channels are compared. |
Bits 7:4 – CMPSEL[3:0] Comparison Selected Channel
If CMPALL = 0: CMPSEL indicates which channel has to be compared.
If CMPALL = 1: No effect.
Bit 2 – CMPTYPE Comparison Type
| Value | Name | Description |
|---|---|---|
| 0 | FLAG_ONLY | Any conversion is performed and comparison function drives the ADC_ISR.COMPE flag. |
| 1 | START_CONDITION | Comparison conditions must be met to start the storage of all conversions until the ADC_CR.CMPRST bit is set. |
Bits 1:0 – CMPMODE[1:0] Comparison Mode
| Value | Name | Description |
|---|---|---|
| 0 | LOW | When the converted data is lower than the low threshold of the window, generates the ADC_ISR.COMPE flag. |
| 1 | HIGH | When the converted data is higher than the high threshold of the window, generates the ADC_ISR.COMPE flag. |
| 2 | IN | When the converted data is in the comparison window, generates the ADC_ISR.COMPE flag. |
| 3 | OUT | When the converted data is out of the comparison window, generates the ADC_ISR.COMPE flag. |