5.2.6.2 Interrupt Software Operations

The LCDC includes two interrupt levels. Specific modules or layers have their own low-level interrupt vector (Base Layer, Overlay 1, Overlay 2, High-End Overlay, Write Protection). Each of their sources can be controlled by an Interrupt Enable register, Interrupt Disable register, and Interrupt Mask register, and can be monitored by an Interrupt Status register. The table below shows the different layers and the registers dedicated to interrupts.

Table 5-2. Low-level Interrupt Register List
ModuleInterrupt Enable RegisterInterrupt Disable RegisterInterrupt Mask RegisterInterrupt Status Register
Base LayerLCDC_BASEIERLCDC_BASEIDRLCDC_BASEIMRLCDC_BASEISR
Overlay 1LCDC_OVR1IERLCDC_OVR1IDRLCDC_OVR1IMRLCDC_OVR1ISR
Overlay 2LCDC_OVR2IERLCDC_OVR2IDRLCDC_OVR2IMRLCDC_OVR2ISR
High-End OverlayLCDC_HEOIERLCDC_HEOIDRLCDC_HEOIMRLCDC_HEOISR
Write Protection–––LCDC_WPSR

Each low-level interrupt is summarized in a single source for the main-level Interrupt vector which is controlled by LCDC_LCDIER, LCDC_LCDIDR and LCDC_LCDIMR, and can be monitored with LCDC_LCDISR. It can be driven by the following sources:

  • Start of frame event
  • LCD disable terminated
  • Display power-up/power-down terminated
  • Configurable active row number event
  • Output FIFO underflow
  • Base Layer interrupt
  • Overlay 1 interrupt
  • Overlay 2 interrupt
  • High-End Overlay interrupt
  • Write Protection interrupt

If any low-level interrupt is triggered, then the main-level interrupt is triggered as well if the source related to the corresponding module is enabled in LCDC_LCDIER. If any main-level interrupt is triggered, then the LCDC interrupt line is raised.

The sequence to clear a low-level interrupt is the following:

  1. Read LCDC_LCDISR and identify the source module.
  2. Read the corresponding low-level Interrupt Status register.
  3. In case of persistent error, take action to stop the error source.
  4. Re-read the corresponding low-level Interrupt Status register to clear it.

Once a low-level interrupt is cleared, the corresponding main-level source is automatically cleared.