8.6.5.7.3 Tx Buffer Element
The Tx Buffers section can be configured to hold dedicated Tx Buffers as well as a Tx FIFO / Tx Queue. In case that the Tx Buffers section is shared by dedicated Tx buffers and a Tx FIFO / Tx Queue, the dedicated Tx Buffers start at the beginning of the Tx Buffers section followed by the buffers assigned to the Tx FIFO or Tx Queue. The Tx Handler distinguishes between dedicated Tx Buffers and Tx FIFO / Tx Queue by evaluating the Tx Buffer configuration TXBC.TFQS and TXBC.NDTB. The element size can be configured for storage of CAN FD messages with up to 64 bytes data field via register TXESC.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||
T0 | ESI | XTD | RTR | ID[28:0] | |||||||||||||||||||||||||||||
T1 | MM[7:0] | EFC | TFCE | FDF | BRS | DLC[3:0] | MM[15:8] | reserved | |||||||||||||||||||||||||
T2 | DB3[7:0] | DB2[7:0] | DB1[7:0] | DB0[7:0] | |||||||||||||||||||||||||||||
T3 | DB7[7:0] | DB6[7:0] | DB5[7:0] | DB4[7:0] | |||||||||||||||||||||||||||||
... | .. | ... | ... | ... | |||||||||||||||||||||||||||||
Tn | DBm[7:0] | DBm-1[7:0]DBM[7:0] | DBm-2[7:0]DBM[7:0] | DBm-3[7:0]DBM[7:0] |
• T0 Bit 30 ESI: Error State Indicator
0: ESI bit in CAN FD format depends only on error passive flag
1: ESI bit in CAN FD format transmitted recessive
• T0 Bit 30 XTD: Extended Identifier
0: 11-bit standard identifier.
1: 29-bit extended identifier.
• T0 Bit 29 RTR: Remote Transmission Request
0: Transmit data frame.
1: Transmit remote frame.
• T0 Bits 28:0 ID[28:0]: Identifier
Standard or extended identifier depending on bit XTD. A standard identifier has to be written to ID[28:18].
• T1 Bits 31:24 MM[7:0]: Message Marker
Written by processor during Tx Buffer configuration. Copied into Tx Event FIFO element for identification of Tx message status.
• T1 Bit 23 EFC: Event FIFO Control
0: Do not store Tx events.
1: Store Tx events.
• T1 Bit 22 TSCE: Timestamp Capture Enable for TSU
Only available when CCCR.UTSU = ‘1’. When this bit is set and the message is transmitted, a pulse is generated to signal the transmission of a Sync message to the Timestamping Unit (TSU) connected to the MCAN.
0: Timestamp Capture disabled
1: Timestamp Capture enabled
• T1 Bit 21 FDF: FD Format
0: Frame transmitted in Classic CAN format
1: Frame transmitted in CAN FD format
• T1 Bit 20 BRS: Bit Rate Switching
0: CAN FD frames transmitted without bit rate switching
1: CAN FD frames transmitted with bit rate switching
Bits ESI, FDF, and BRS are only evaluated when CAN FD operation is enabled (MCAN_CCCR.FDOE = 1). Bit BRS is only evaluated when in addition MCAN_CCCR.BRSE = 1.
• T1 Bits 19:16 DLC[3:0]: Data Length Code
0-8: CAN + CAN FD: transmit frame has 0-8 data bytes.
9-15: CAN: transmit frame has 8 data bytes.
9-15: CAN FD: transmit frame has 12/16/20/24/32/48/64 data bytes.
• T1 Bits 15:8 MM[15:8]: Message Marker
High byte of Wide Message Marker, written by CPU during Tx Buffer configuration. Copied into Tx Event FIFO element for identification of Tx message status. Available only when CCCR.WMM = ‘1’ or when CCCR.UTSU = ‘1’.
• T2 Bits 31:24 DB3[7:0]: Data Byte 3
• T2 Bits 23:16 DB2[7:0]: Data Byte 2
• T2 Bits 15:8 DB1[7:0]: Data Byte 1
• T2 Bits 7:0 DB0[7:0]: Data Byte 0
• T3 Bits 31:24 DB7[7:0]: Data Byte 7
• T3 Bits 23:16 DB6[7:0]: Data Byte 6
• T3 Bits 15:8 DB5[7:0]: Data Byte 5
• T3 Bits 7:0 DB4[7:0]: Data Byte 4
... ... ...
• Tn Bits 31:24 DBm[7:0]: Data Byte m
• Tn Bits 23:16 DBm-1[7:0]: Data Byte m-1
• Tn Bits 15:8 DBm-2[7:0]: Data Byte m-2
• Tn Bits 7:0 DBm-3[7:0]: Data Byte m-3